XR16M554 Datasheet, PDF (46/46 Pages) Exar Corporation – 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO

XR16M554/554D
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
REV. 1.0.0
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 28
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE................................................. 28
TABLE 13: UART RESET CONDITIONS FOR CHANNELS A-D .................................................................................................. 29
ABSOLUTE MAXIMUM RATINGS.................................................................................. 30
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 30
ELECTRICAL CHARACTERISTICS ............................................................................... 30
DC ELECTRICAL CHARACTERISTICS ............................................................................................................. 30
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 31
TA = -40O TO +85OC, VCC IS 1.62 TO 3.63V, 70 PF LOAD WHERE APPLICABLE ........................................... 31
FIGURE 12. CLOCK TIMING............................................................................................................................................................. 32
FIGURE 13. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D .................................................................................................... 33
FIGURE 14. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D.................................................................................... 33
FIGURE 15. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D .................................................................................. 34
FIGURE 16. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D........................................................................... 34
FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D ............................................................ 35
FIGURE 17. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D ......................................................................... 35
FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D .......................................................... 36
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D........................................... 36
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D............................................ 37
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D............................... 37
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D ............................... 38
PACKAGE DIMENSIONS ................................................................................................................................ 39
REVISION HISTORY...................................................................................................................................... 43
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