XR16M554 Datasheet, PDF (20/46 Pages) Exar Corporation – 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO

XR16M554/554D
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
REV. 1.0.0
TABLE 8: INTERNAL REGISTERS DESCRIPTION.
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 1 IER RD/WR 0
0
0
0 1 0 ISR RD FIFOs FIFOs
0
Enabled Enabled
0
Modem RX Line TX
RX
Stat. Int. Stat. Empty Data
Enable Int.
Int
Int.
Enable Enable Enable _{LCR[7] = 0}
0
INT
INT INT INT
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
0 1 0 FCR WR RX FIFO RX FIFO 0
Trigger Trigger
0
DMA
TX
RX FIFOs
Mode FIFO FIFO Enable
Enable Reset Reset
011
LCR RD/WR Divisor Set TX Set
Enable Break _Parity
Even
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
1 0 0 MCR RD/WR 0
0
0
Internal INT Rsvd RTS# DTR#
Lopback _{Output (OP1#)} Output Output
Enable _Enable
Control Control
(OP2#)
101
LSR RD/WR RX
FIFO
Global
Error
THR &
TSR
Empty
THR RX Break RX
Empty
Framing
Error
RX
Parity
Error
RX
Over-
run
Error
RX
Data _{LCR[7] = 0}
Ready
110
MSR RD/WR CD# RI# Input DSR#
Input
Input
CTS#
Input
Delta
CD#
Delta Delta Delta
RI# DSR# CTS#
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
Baud Rate Generator Divisor
000
001
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0 LCR[7]=1
Bit-0 ^{LCR≠0xBF}
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 16.
4.2 Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 14.
4.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
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