XR16M554 Datasheet, PDF (45/46 Pages) Exar Corporation – 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO

REV. 1.0.0
XR16M554/554D
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS .............................................................................................................................................. 1
FIGURE 1. XR16M554 BLOCK DIAGRAM .......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES ......................... 2
FIGURE 3. PIN OUT ASSIGNMENT FOR 48-PIN QFN PACKAGE AND 80-PIN LQFP PACKAGE............................................................... 3
PIN DESCRIPTIONS ......................................................................................................... 4
ORDERING INFORMATION ............................................................................................................................... 4
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 9
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 10
2.1 CPU INTERFACE .............................................................................................................................................. 10
FIGURE 4. XR16M554 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS .......................................................................... 10
2.2 DEVICE RESET ................................................................................................................................................. 11
2.3 CHANNEL SELECTION .................................................................................................................................... 11
TABLE 1: CHANNEL A-D SELECT IN 16 MODE ................................................................................................................................. 11
TABLE 2: CHANNEL A-D SELECT IN 68 MODE ................................................................................................................................. 11
2.4 CHANNELS A-D INTERNAL REGISTERS ....................................................................................................... 12
2.5 INT OUPUTS FOR CHANNELS A-D................................................................................................................. 12
TABLE 3: INT PIN OPERATION FOR TRANSMITTER FOR CHANNELS A-D ........................................................................................... 12
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D ................................................................................................. 12
2.6 DMA MODE ....................................................................................................................................................... 12
TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D ........................................................... 13
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 13
FIGURE 5. TYPICAL CRYSTAL CONNECTIONS .................................................................................................................................. 13
2.8 PROGRAMMABLE BAUD RATE GENERATOR.............................................................................................. 13
FIGURE 6. BAUD RATE GENERATOR ............................................................................................................................................... 14
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 14
2.9 TRANSMITTER.................................................................................................................................................. 14
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 15
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 15
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 15
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 15
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 15
2.10 RECEIVER ....................................................................................................................................................... 16
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 16
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 16
FIGURE 10. RECEIVER OPERATION IN FIFO.................................................................................................................................... 17
2.11 INTERNAL LOOPBACK................................................................................................................................. 18
FIGURE 11. INTERNAL LOOP BACK IN CHANNELS A - D ................................................................................................................... 18
3.0 UART INTERNAL REGISTERS............................................................................................................. 19
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS ...................................................................................... 19
TABLE 8: INTERNAL REGISTERS DESCRIPTION. ................................................................................................................... 20
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 20
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 20
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 20
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 20
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 21
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 21
4.4 INTERRUPT STATUS REGISTER (ISR)........................................................................................................... 22
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 22
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 22
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 22
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 23
TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION ................................................................................................................... 23
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 24
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 25
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE . 25
TABLE 12: INT OUTPUT MODES ..................................................................................................................................................... 26
4.8 LINE STATUS REGISTER (LSR) - READ/WRITE ............................................................................................ 26
4.9 MODEM STATUS REGISTER (MSR) - READ/WRITE...................................................................................... 27
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