XRT75L00 Datasheet, PDF (45/50 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

REV. 1.0.2
ADDRESS
(HEX)
TYPE
BIT LOCATION
0x08
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 16: REGISTER MAP DESCRIPTION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
Reserved
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL
ADDRESS
(HEX)
0x20
TYPE
R/W
0x21
Read
Only
0x22 -
0x2F
0x30
0x31
0x32-
0x37
0x38
0x39-
0x3D
0x3E
0x3F
Reset
Upon
Read
Reset
Upon
Read
Read
Only
Read
Only
Read
Only
BIT
LOCATION
D0
D0
SYMBOL
INTEN
INTST
DESCRIPTION
DEFAULT
VALUE(BIN)
Bit 0 = INTEN Writing a “1” to this bit enables the
0
interrupts.
Bit 0 = INTST bit is set to “1” if an interrupt service is
0
required. The source level interrupt status register is
read to determine the cause of interrupt.
Reserved
D[7:0]
PRBSmsb PRBS error counter MSB [15:8]
D[7:0]
PRBSlsb PRBS error counter LSB [7:0]
Reserved
D[7:0]
PRBShold PRBS Holding Register
Reserved
D[7:0]
Chip_id This read only register contains device id.
01110001
D[7:0] Chip_version This read only register contains chip version number 00000001
43