XRT75L00 Datasheet, PDF (38/50 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL is set to “1”
in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts
of jitter.
Table 13 specifies the jitter transfer mask requirements for various data rates.
RATE
(KBITS)
34368
44736
51840
MASK
G.823
ETSI-TBR-24
GR-499, Cat I
GR-499, Cat II
GR-253 CORE
GR-253 CORE
TABLE 13: JITTER TRANSFER PASS MASKS
F1
F2
F3
F4
(HZ)
(HZ)
(HZ)
(KHZ)
100
300
3K
800K
10
10k
-
15k
10
56.6k
-
300k
10
40
-
15k
10
40k
-
400k
A1(dB)
0.5
0.1
0.1
0.1
0.1
A2(dB)
-19.5
-
-
-
-
The jitter attenuator within the XRT75L00 meets the latest jitter attenuation specifications and/or jitter transfer
characteristics as shown in the Figure 24.
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
A1
A2
F1
F2
F3
F4
JITTER FREQ UENCY (kHz)
36