XRT75L00 Datasheet, PDF (42/50 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
0x02 Reset
D0
Upon
Read
DMOIS This bit is set to “1” every time a DMO status change
0
has occurred since the last cleared interrupt.This bit
is cleared when read.
D1
RLOSIS This bit is set to “1” every time a RLOS status change
0
has occurred since the last cleared interrupt. This bit
is cleared when read.
D2
RLOLIS This bit is set to “1” every time a RLOL status change
0
has occurred since the last cleared interrupt. This bit
is cleared when read.
D3
FLIS
This bit is set to “1” every time a FIFO Limit status
0
change has occurred since the last cleared interrupt.
This bit is cleared when read.
D4
PRBSIS This bit is set to “1” when a PRBS bit error is
0
detected. This bit is cleared when read.
D5
CNT_SATIS This bit is set to “1” when the PRBS error counter has
0
saturated (0xFFFF). This bit is cleared when read.
0x03 Read
D0
Only
DMO
This bit is set to “1” every time the MTIP/MRing input
0
pins have not detected any bipolar pulses for 128
consecutive bit periods.
D1
RLOS This bit is set to “1” every time the receiver declares
0
an LOS condition.
D2
RLOL This bit is set to “1” every time when the receiver
0
declares a Loss of Lock condition.
D3
FL
This bit is set to “1” every time the FIFO in the Jitter
0
Attenuator is within 2 bit of underflow/overflow condi-
tion.
D4
ALOS This bit is set to “1” every time the receiver declares
0
Analog LOS condition.
D5
DLOS This bit is set to “1” every time the receiver declares
0
Digital LOS condition.
D6
PRBSLS This bit is set to “1” every time the PRBS detects a bit
0
error.
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