XRT73LC03A Datasheet, PDF (41/61 Pages) Exar Corporation – 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
Decoder detects this particular pattern, then it substi-
tutes these bits with a “0000" pattern.
Figure 25 illustrates the HDB3 Decoder at work with
two separate Zero Suppression patterns, in the in-
coming Dual-Rail Data Stream.
FIGURE 25. AN EXAMPLE OF HDB3 DECODING
Line Signal
00 0 V
RCLK
B 00 V
RPOS
RNEG
Data 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
NOTE: If the HDB3 Decoder detects any bipolar violation
(e.g., "V") pulses that is not in accordance with the HDB3
Line Code format, or if the HDB3 Decoder detects a string
of 4 (or more) "0’s" in the incoming line signal, then the
HDB3 Decoder flags this event as a Line Code Violation by
pulsing the LCV output pin “High".
3.4.3 Configuring the HDB3/B3ZS Decoder
The XRT73LC03A can enable or disable the HDB3/
B3ZS Decoder blocks by either of the following
means.
a. Operating in the HOST Mode
Enable the HDB3/B3ZS Decoder block of Channel(n)
by writing a "0" into the (SR/DR)_(n) bit-field within
Command Register CR3-(n), as illustrated below.
COMMAND REGISTER CR2-(n)
D4
D3
D2
D1
D0
Reserved
ENDECDIS_(n)
ALOSDIS_(n)
DLOSDIS_(n)
REQEN_(n)
X
0
X
X
1
b. Operating in the Hardware Mode
To globally enable all HDB3/B3ZS Decoder blocks in
the XRT73LC03A, pull the ENDECDIS input pin
“Low". To globally disable all HDB3/B3ZS Decoder
blocks in the XRT73LC03A and configure the
XRT73LC03A to transmit and receive in an AMI for-
mat, pull the ENDECDIS input pin "High".
3.5 LOS DECLARATION/CLEARANCE
Each channel of the XRT73LC03A contains circuitry
that monitors the following two parameters associat-
ed with the incoming line signals.
1. The amplitude of the incoming line signal via the
RTIP and RRing inputs.
2. The number of pulses detected in the incoming
line signal within a certain amount of time.
If a given channel of the XRT73LC03A determines
that the incoming line signal is missing due to either
insufficient amplitude or a lack of pulses in the incom-
ing line signal, it declares a Loss of Signal (LOS) con-
dition. The channel declares the LOS condition by
toggling its respective RLOS_(n) output pin “High”
and by setting its corresponding RLOS_(n) bit field in
Command Register 0 or Command Register 8 to "1".
Conversely, if the channel determines that the incom-
ing line signal has been restored (e.g., there is suffi-
cient amplitude and pulses in the incoming line sig-
nal), it clears the LOS condition by toggling its re-
spective RLOS_(n) output pin "Low" and setting its
corresponding RLOS_(n) bit-field to "0".
In general, the LOS Declaration/Clearance scheme
that is employed in the XRT73LC03A is based upon
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