XRT73LC03A Datasheet, PDF(30/61 Page) Exar Corporation – 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

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XRT73LC03A Datasheet, PDF (30/61 Pages) Exar Corporation – 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

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XRT73LC03A

3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

REV. 1.0.1

FIGURE 14. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FOR-

MAT FROM THE TRANSMITTING TERMINAL EQUIPMENT TO THE TRANSMIT SECTION OF A CHANNEL

Terminal

Equipment

(E3/DS3 or STS-1

Framer)

TxPOS

TxNEG

TxLineClk

TPData

TNData

TxClk

Transmit

Logic

Block

Exar E3/DS3/STS-1 LIU

The manner that the LIU handles Dual-Rail data is

described below and illustrated in Figure 15. The

Transmit Section (of a Channel) typically samples the

data on the TPData_(n) and TNData_(n) input pins

on the falling edge of TxClk_(n).

FIGURE 15. THE XRT73LC03A SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS

Data

TPData

TNData

TxClk

TxClk_(n) is the clock signal that is of the selected

data rate frequency, E3 = 34.368 MHz, DS3 = 44.736

MHz and STS-1 = 51.84 MHz. If the Transmit Section

samples a "1" on the TPData_(n) input pin, then the

Transmit Section of the device ultimately generates a

positive polarity pulse via the TTIP_(n) and TRing_(n)

output pins across a 1:1 transformer. If the Transmit

Section samples a "1" on the TNData_(n) input pin,

then the Transmit Section of the device ultimately

generates a negative polarity pulse via the TTIP_(n)

and TRing_(n) output pins across a 1:1 transformer.

2.1.2 Accepting Single-Rail Data from the Ter-

minal Equipment

To transmit data in a Single-Rail data from the Termi-

nal Equipment, configure the XRT73LC03A in the

HOST Mode.

Write a "1" into the TxBin_(n) (TRANSMIT BINary)

bit-field of Command Register CR1-(n) shown below.

NOTE: Please refer to Table 2 for the Address of the indi-

vidual Channel(n).

COMMAND REGISTER CR1-(n)

TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBin_(n)

The Transmit Section of each channel samples this

input pin on the falling edge of the TxClk_(n) clock

signal and encodes this data into the appropriate bi-

polar line signal across the TTIP_(n) and TRing_(n)

output pins.

NOTES:

1. In this mode, the Transmit Logic Block ignores the

TNData_(n) input pin.

▷