XR16L2751 Datasheet, PDF (41/52 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
áç
asleep. Floating inputs may result in sleep currents in the mA range. For Powersave, the UART internally
isolates all of these inputs therefore not requiring them to remain steady.
AC ELECTRICAL CHARACTERISTICS
TA=0^O TO 70^OC (-40^O TO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.5- 5.0V +/-10%
SYMBOL
PARAMETER
LIMITS
2.5
MIN
MAX
LIMITS
3.3
MIN
MAX
LIMITS
5.0
MIN
MAX
UNIT
CONDITIONS
CLK Clock Pulse Duration
50
50
17
ns
OSC Oscillator Frequency
16
20
24 MHz
OSC External Clock Frequency
24
33
50 MHz
T_AS Address Setup Time (16 Mode) 15
10
5
ns
T_AH Address Hold Time (16 Mode)
15
10
5
ns
T_CS Chip Select Width (16 Mode)
66
66
50
ns
T_RD IOR# Strobe Width (16 Mode)
50
35
25
ns
T_DY Read Cycle Delay (16 Mode)
50
40
30
ns
T_RDV Data Access Time (16 Mode)
50
50
35 ns
T_DD Data Disable Time (16 Mode)
0
35
0
35
0
25 ns
T_WR IOW# Strobe Width (16 Mode)
40
40
25
ns
T_DY Write Cycle Delay (16 Mode)
50
40
30
ns
T_DS Data Setup Time (16 Mode)
15
10
5
ns
T_DH Data Hold Time (16 Mode)
15
10
5
ns
T_{ADS Address Setup (68 Mode)}
15
10
5
ns
T_{ADH Address Hold (68 Mode)}
15
10
5
ns
T_{RWS R/W# Setup to CS# (68 Mode)}
15
10
5
ns
T_{RDA Read Data Access (68 mode)}
50
45
35
ns
T_{RDH Read Data Hold (68 mode)}
35
30
25
ns
T_{WDS Write Data Setup (68 mode)}
15
10
5
ns
T_{WDH Write Data Hold (68 Mode)}
15
10
5
ns
T_{RWH CS# De-asserted to R/W# De-}
15
10
asserted (68 Mode)
5
ns
T_{CSL CS# Width (68 Mode)}
50
40
30
ns
T_{CSD CS# Cycle Delay (68 Mode)}
50
40
30
ns
T_WDO Delay From IOW# To Output
50
50
40 ns 100 pF load
T_MOD Delay To Set Interrupt From
MODEM Input
50
40
35 ns 100 pF load
41