XR16L2751 Datasheet, PDF (10/52 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

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XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
Beyond the general 16C2550 features and capabilities, the 2751 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, FCTR, TRG, EMSR, FC) that provide automatic RTS and CTS hardware flow control, Xon/
Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger level
control and FIFO level counters. All the register functions are discussed in full detail later in “Section 3.0, UART
INTERNAL REGISTERS” on page 22.
2.7 DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFO are enabled and the DMA mode
is disabled (FCR bit-3 = 0), the 2751 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the 2751
sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see Figures 20 through 25.
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
RXRDY# A/B 0 = 1 byte.
1 = no data.
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
0 = at least 1 byte in FIFO.
1 = FIFO empty.
FCR Bit-3 = 1
(DMA Mode Enabled)
1 to 0 transition when FIFO reaches the trigger
level, or time-out occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B 0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
2.8 INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and 5 summarize the operating behavior for the transmitter and receiver. Also see Figures 20
through 25.
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INTA/B Pin
NO
0 = a byte in THR
1 = THR empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
INTA/B Pin
YES
0 = a byte in THR
1 = transmitter empty
0 = FIFO above trigger level
1 = FIFO below trigger level or transmitter empty
INTA/B Pin
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
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