XR16L2751 Datasheet, PDF (20/52 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

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XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
2.20 Sleep Mode with Auto Wake-Up and PowerSave Feature
The 2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave
features is included to reduce power consumption when the device is not actively used. The PowerSave feature
is enabled by connecting pin 12 to VCC. It further saves power consumption by isolating its data bus from other
bus activities that could cause wasteful power drain. This is particularly useful when the system design does
not have buffers for the address and data lines.
With EFR bit-4 and IER bit-4 of both channels enabled (set to a logic 1), the 2751 DUART enters sleep mode
when no interrupt is pending for both channels. The 2751 stops its crystal oscillator to further conserve power
in the sleep mode. User can check the XTAL2 pin for no clock output as an indication that the device has
entered the sleep mode.
Once entered into the sleep mode, the host can still communicate with the 2751 if the PowerSave mode is not
enabled by having pin 12 at ground. However, if PowerSave mode is enabled with pin 12 at VCC then the host
will not be able to communicate with the 2751 because of the isolation on its interface signals.
The 2751 resumes normal operation by any of the following when PowerSave mode is disabled (pin 12 at
ground): a receive data start bit transition (logic 1 to 0), a data byte is loaded to the transmitter, THR or FIFO, a
change of logic state on any of the modem or general purpose serial inputs; CTS#, DSR#, CD#, RI#. However,
if PowerSave mode is enabled, the only way to wake-up the device is through its modem input signals or a
receive data start bit. That is because its data bus interface is isolated. Figure 1 shows the PowerSave isolating
signals.
If the 2751 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the 2750 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
an interrupt is pending from channel A or B. The 2751 will stay in the sleep mode of operation until it is disabled
by setting IER bit-4 to a logic 0.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. The number of characters lost during the restart also depends on your
operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep
RX A/B inputs idling at logic 1 or “marking” condition during sleep mode to avoid receiving a “break” condition
upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)
are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a
47k-100k ohm pull-up resistor on the RXA and RXB pins.
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