XR16L2751 Datasheet, PDF (3/52 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
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PIN DESCRIPTIONS
Pin Description
NAME
48-TQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2:A0
26,27,28
I _{Address data lines [2:0]. These 3 address lines select one of the internal registers in}
UART channel A/B during a data bus transaction.
D7:D0
IOR#
(VCC)
3, 2, 1, 48, 47, I/O _{Data bus lines [7:0] (bidirectional).}
46, 45, 44
19
I _{When 16/68# pin is at logic 1, the Intel bus interface is selected and this input}
becomes read strobe (active low). The falling edge instigates an internal read cycle
and retrieves the data byte from an internal register pointed by the address lines
[A2:A0], puts the data byte on the data bus to allow the host processor to read it on
the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is
not used and should be connected to VCC.
IOW#
15
I _{When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes}
(R/W#)
write strobe (active low). The falling edge instigates the internal write cycle and the
rising edge transfers the data byte on the data bus to an internal register pointed by
the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input
becomes read (logic 1) and write (logic 0) signal.
CSA#
(CS#)
10
I _{When 16/68# pin is at logic 1, this input is chip select A (active low) to enable channel}
A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select (active low) for the
Motorola bus interface.
CSB#
(A3)
11
I _{When 16/68# pin is at logic 1, this input is chip select B (active low) to enable channel}
B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3 which is used for
channel selection in the Motorola bus interface. Input logic 0 selects channel A and
logic 1 selects channel B.
INTA
(IRQ#)
30
O _{When 16/68# pin is at logic 1 for Intel bus interface, this output becomes channel A}
interrupt output. The output state is defined by the user through the software setting
of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when
MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes device
interrupt output (active low, open drain). An external pull-up resistor is required for
proper operation.
INTB
29
O _{When 16/68# pin is at logic 1 for Intel bus interface, this output becomes channel B}
interrupt output. The output state is defined by the user and through the software set-
ting of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when
MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output is not used and
will stay at logic zero level. Leave this output unconnected.
TXRDYA#
43
O _{UART channel A Transmitter Ready (active low). The output provides the TX FIFO/}
THR status for transmit channel A.
3