XRT75L06D Datasheet, PDF (4/103 Pages) Exar Corporation – SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L06D
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.4
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................ 1
APPLICATIONS............................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L06D............................................................................................................................ 1
ORDERING INFORMATION.................................................................................................................... 1
FEATURES .................................................................................................................................................... 2
TRANSMIT INTERFACE CHARACTERISTICS....................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS......................................................................................................... 2
FIGURE 2. XRT75L06D IN BGA PACKAGE (BOTTOM VIEW) .............................................................................................................. 3
TABLE OF CONTENTS...................................................................................................... I
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
TRANSMIT INTERFACE.................................................................................................................................... 4
RECEIVE INTERFACE...................................................................................................................................... 6
CLOCK INTERFACE ........................................................................................................................................ 8
CONTROL AND ALARM INTERFACE ....................................................................................................... 9
ANALOG POWER AND GROUND .................................................................................................................... 12
DIGITAL POWER AND GROUND ..................................................................................................................... 14
1.0 CLOCK SYNTHESIZER ......................................................................................................................... 16
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE INPUT CLOCK CIRCUITRY DRIVING THE MICROPROCESSOR ...................................... 16
1.1 CLOCK DISTRIBUTION .................................................................................................................................... 16
FIGURE 4. CLOCK DISTRIBUTION CONGIFURED IN E3 MODE WITHOUT USING SFM.......................................................................... 16
2.0 THE RECEIVER SECTION .................................................................................................................... 17
FIGURE 5. RECEIVE PATH BLOCK DIAGRAM .................................................................................................................................... 17
2.1 RECEIVE LINE INTERFACE ............................................................................................................................. 17
FIGURE 6. RECEIVE LINE INTERFACECONNECTION .......................................................................................................................... 17
2.2 ADAPTIVE GAIN CONTROL (AGC) ................................................................................................................. 18
2.3 RECEIVE EQUALIZER ...................................................................................................................................... 18
FIGURE 7. ACG/EQUALIZER BLCOK DIAGRAM................................................................................................................................. 18
2.3.1 RECOMMENDATIONS FOR EQUALIZER SETTINGS ................................................................................................ 18
2.4 CLOCK AND DATA RECOVERY ...................................................................................................................... 18
2.4.1 DATA/CLOCK RECOVERY MODE .............................................................................................................................. 18
2.4.2 TRAINING MODE.......................................................................................................................................................... 18
2.5 LOS (LOSS OF SIGNAL) DETECTOR.............................................................................................................. 19
2.5.1 DS3/STS-1 LOS CONDITION ....................................................................................................................................... 19
TABLE 1: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3
AND STS-1 APPLICATIONS) ............................................................................................................................................ 19
2.5.2 DISABLING ALOS/DLOS DETECTION ....................................................................................................................... 19
2.5.3 E3 LOS CONDITION:.................................................................................................................................................... 20
FIGURE 8. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775 ............................................................................................ 20
FIGURE 9. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775. ........................................................................................... 20
2.5.4 INTERFERENCE TOLERANCE.................................................................................................................................... 21
FIGURE 10. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1................................................................................................ 21
FIGURE 11. INTERFERENCE MARGIN TEST SET UP FOR E3.............................................................................................................. 21
TABLE 2: INTERFERENCE MARGIN TEST RESULTS ........................................................................................................................... 22
2.5.5 MUTING THE RECOVERED DATA WITH LOS CONDITION: ..................................................................................... 23
FIGURE 12. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING ................................................................................................. 23
2.6 B3ZS/HDB3 DECODER..................................................................................................................................... 23
3.0 THE TRANSMITTER SECTION ............................................................................................................. 24
FIGURE 13. TRANSMIT PATH BLOCK DIAGRAM ................................................................................................................................ 24
3.1 TRANSMIT DIGITAL INPUT INTERFACE ........................................................................................................ 24
FIGURE 14. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75L06D (DUAL-RAIL DATA) ...................................... 24
FIGURE 15. TRANSMITTER TERMINAL INPUT TIMING ........................................................................................................................ 25
FIGURE 16. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED) ............................................................ 25
3.2 TRANSMIT CLOCK ........................................................................................................................................... 26
3.3 B3ZS/HDB3 ENCODER..................................................................................................................................... 26
3.3.1 B3ZS ENCODING ......................................................................................................................................................... 26
FIGURE 18. B3ZS ENCODING FORMAT ........................................................................................................................................... 26
3.3.2 HDB3 ENCODING......................................................................................................................................................... 26
FIGURE 17. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED) ............................................................................. 26
FIGURE 19. HDB3 ENCODING FORMAT .......................................................................................................................................... 27
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