XRT75L06D Datasheet, PDF (14/103 Pages) Exar Corporation – SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L06D
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.4
CONTROL AND ALARM INTERFACE
C9
RLOL_0
O Receive Loss of Lock - Channel 0:
T8
RLOL_1
D12
RLOL_2
R11
RLOL_3
C11
RLOL_4
R9
RLOL_5
Receive Loss of Lock - Channel 1:
Receive Loss of Lock - Channel 2:
Receive Loss of Lock - Channel 3:
Receive Loss of Lock - Channel 4:
Receive Loss of Lock - Channel 5:
This output pin toggles "High" if a Loss of Lock Condition is detected. LOL
(Loss of Lock) condition occurs if the recovered clock frequency deviates from
the Reference Clock frequency (available at either E3CLK or DS3CLK or STS-
1CLK input pins) by more than 0.5%.
L16
RXA
**** External Resistor of 3.01K Ω ± 1%.
Should be connected between RxA and RxB for internal bias.
K16
RXB
**** External Resistor of 3.01K Ω ±1%.
Should be connected between RxA and RxB for internal bias.
P12
ICT
I In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. For normal operation, tie this pin
"High".
NOTE: This pin is internally pulled up.
R12
TEST
**** Factory Test Pin
NOTE: This pin must be connected to GND for normal operation.
MICROPROCESSOR INTERFACE
LEAD #
K3
SIGNAL
NAME
CS
TYPE
DESCRIPTION
I Chip Select
Tie this “Low” to enable the communication with the Microprocessor Interface.
R1
PCLK
I Processor Clock Input
To operate the Microprocessor Interface, appropriate clock frequency is pro-
vided through this pin. Maximum frequency is 66 Mhz.
K2
WR
I Write Data :
To write data into the registers, this active low signal is asserted.
L2
RD
I Read Data:
To read data from the registers, this active low pin is asserted.
J3
RESET
I Register Reset:
Setting this input pin "Low" resets the contents of the Command Registers to
their default settings and default operating configuration
NOTE: This pin is internally pulled up.
L3
PMODE
I Processor Mode Select:
When this pin is tied “High”, the microprocessor is operating in synchronous
mode which means that clock must be applied to the PCLK (pin 55).
Tie this pin “Low” to select the Asynchronous mode. An internal clock is pro-
vided for the microprocessor interface.
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