XRK39910 Datasheet, PDF (4/9 Pages) Exar Corporation – 3.3V LOW SKEW PLL CLOCK DRIVER

XRK39910
3.3V LOW SKEW PLL CLOCK DRIVER
TABLE 6: DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
CONDITIONS
MIN.
I3 3-Level Input DC Current (BYPASS, FSEL) VIN = VDD
VIN = VDD/2
HIGH Level
MID Level
IPU Input Pull-Up current (PE)
VIN = GND
LOW Level
VDD = Max., VIN = GND
IPD Input Pull-Down Current (OE)
VOH Output HIGH Voltage
VDD= Max., VIN = VDD
VDD = Min., IOH = -12mA
2.4
VOL Output LOW Voltage
VDD = Min., IOL = 12mA
REV. 1.0.0
MAX.
+400
+200
+400
+100
+100
0.55
UNIT
μA
μA
μA
V
V
NOTE: (1) These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected
inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL
may require an additional tLOCK time before all datasheet limits are achieved.
TABLE 7: POWER SUPPLY CHARACTERISTICS
SYMBOL
PARAMETER
IDDQ Quiescent Power Supply Current
TEST CONDITIONS(1)
TYP.
VDD=Max., BYPASS=MID, CLKIN=LOW 8
VDD/PE=LOW, OE=LOW,
All outputs unloaded
ITOT Total Power Supply Current
VDD=3.3V, FREF=25MHz, CL=160pF⁽¹⁾
34
VDD=3.3V, FREF=33MHz, CL=160pF⁽¹⁾
42
VDD=3.3V, FREF=66MHz, CL=160pF⁽¹⁾
76
MAX.
25
UNIT
mA
mA
NOTE: (1) For eight outputs, each loaded with 20pF.
SYMBOL
tR, tF
tPWC
DH
Ref
TABLE 8: INPUT TIMING REQUIREMENTS
DESCRIPTION(1)
MIN.
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
3
Input duty cycle
10
Reference Clock Input
15
NOTE: (1) Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
MAX.
10
90
85
UNIT
ns/V
ns
%
MHz
4