XRK39910 Datasheet, PDF (3/9 Pages) Exar Corporation – 3.3V LOW SKEW PLL CLOCK DRIVER

REV. 1.0.0
XRK39910
3.3V LOW SKEW PLL CLOCK DRIVER
TABLE 4: PIN DESCRIPTIONS
PIN NAME PIN NUMBER TYPE
DESCRIPTION
Q0 - Q7
7,8,10,11, OUT Eight clock output.
15,16,18,19
GND
9,17,24 PWR Ground.
FB_IN
13
IN Feedback Input
OE⁽²⁾
21
IN Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and
Q3) in a LOW state - Q2 and Q3 may be used as the feedback signal to maintain
phase lock. Set OE LOW for normal operation.
BYPASS^(1,2)
23
IN When MID or HIGH, disable PLL (except for conditions of Note 2). CLKIN goes to
all outputs. Set LOW for normal operations.
NOTE:
1.
2.
3.
Tri-Level Input
When BYPASS = MID and OE = HIGH, PLL remains active.
This input is wired to VDD, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the
outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved.
TABLE 5: RECOMMENDED OPERATING RANGE
SYMBOL
DESCRIPTION
XRK39910-2, -5, -7
(INDUSTRIAL)
MIN.
MAX.
XRK39910-2, -5, -7
(COMMERCIAL)
MIN.
MAX.
VDD Power Supply Voltage
3
3.6
3
3.6
TA
Ambient Operating Temperature
-40
+85
0
+70
UNIT
V
°C
TABLE 6: DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VIH Input HIGH Voltage
Guranteed Logic HIGH
2
V
(CLKIN, FB_IN, OE, PE Inputs
Only)
VIL Input LOW Voltage
Guaranteed Logic LOW
(CLKIN, FB_IN, OE, PE Inputs
Only)
0.8
V
VIHH _{Input HIGH Voltage} ⁽¹⁾
3-Level Inputs Only
VDD-0.6
V
(FSEL, BYPASS)
VIMM _{Input MID Voltage} ⁽¹⁾
3-Level Inputs Only
(FSEL, BYPASS)
VDD/2-0.3 VDD/2+0.3 V
VILL _{Input LOW Voltage} ⁽¹⁾
3-Level Inputs Only
(FSEL, BYPASS)
0.6
V
IIN Input Leakage Current
(CLKIN, FB_IN Inputs Only)
VIN = VDD or GND
VDD = Max.
+5
μA
3