XRK39910 Datasheet, PDF (2/9 Pages) Exar Corporation – 3.3V LOW SKEW PLL CLOCK DRIVER

XRK39910
3.3V LOW SKEW PLL CLOCK DRIVER
PRODUCT NUMBER
XRK39910CD-2
XRK39910ID-2
XRK39910CD-5
XRK39910ID-5
XRK39910CD-7
XRK39910ID-7
TABLE 1: ORDERING INFORMATION
ACCURACY
250ps
250ps
500ps
500ps
750ps
750ps
REV. 1.0.0
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
SYMBOL
V_I
TSTG
TABLE 2: ABSOLUTE MAXIMUM RATINGS(1)
DESCRIPTION
MAX
Supply Voltage to Ground
-0.5 to +7
DC Input Voltage
-0.5 to VDD+0.5
CLKIN Input Voltage
-0.5 to +5.5
Maximum Power Dissipation (TA = 85°C)
Storage Temperature
530
-65 to +150
UNIT
V
V
V
mW
°C
NOTE: (1) Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum-rated
conditions for extended periods may affect device reliability.
PARAMETER
CIN
TABLE 3: CAPACITANCE (TA= +25°C, f= 1MHZ, VIN= 0V)
DESCRIPTION
TYP
MAX
Input Capacitance
5
7
UNIT
pF
NOTE: Capacitance applies to all inputs except BYPASS and FSEL. It is characterized but not production tested
.
TABLE 4: PIN DESCRIPTIONS
PIN NAME PIN NUMBER TYPE
DESCRIPTION
CLKIN
1
IN Reference Clock Input
VDDPLL
2
PWR Power supply for phase locked loop and other internal circuitry.
FSEL^(1,3)
3
IN Frequency range select: FSEL = GND:15 to 35MHz
FSEL = MID (or open): 25 to 60MHz
FSEL = VDD: 40 to 85MHz
PE
5
IN Selectable positive or negative edge control. When LOW/HIGH the outputs are
synchronized with the negative/positive edge of the reference clock.
VDD
6,12,14,20 PWR Power supply for output buffers.
2