XRK39910 Datasheet, PDF (1/9 Pages) Exar Corporation – 3.3V LOW SKEW PLL CLOCK DRIVER

JULY 2006
FUNCTIONAL DESCRIPTION
The XRK39910 is a high fanout phase locked-loop
clock driver intended for high performance computing
and data-communications applications. It has eight
zero delay LVTTL outputs.
When the OE pin is held low, all the outputs are syn-
chronously enabled. However, if OE is held high, all
the outputs except Q2 and Q3 are synchronously dis-
abled.
Furthermore, when the PE is held high, all the outputs
are synchronized with the positive edge of the CLKIN.
When PE is held low, all the outputs are synchronized
with the negative edge of CLKIN.
The FB_IN signal is compared with the input CLKIN
signal at the phase detector in order to drive the
VCO. Phase differences cause the VCO of the PLL to
adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the
VCO to the phase detector. The loop filter transfer
function has been chosen to provide minimal jitter (or
frequency variation) while still providing accurate
responses to input frequency changes.
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
Q0
H
Q1
M
CLKIN
Ref
VCO
L
Q2
PLL
Q3
FB_IN
Feedback
Q4
FSEL*
Q5
PE
Bypass*
Q6
Q7
OE
* Tri-Level inputs
XRK39910
3.3V LOW SKEW PLL CLOCK DRIVER
REV. 1.0.0
FEATURES
• Eight zero delay outputs
• 12mA balanced drive outputs
• Output frequency: 15MHz to 85MHz
• <250ps of output to output skew
• Low Jitter: <200ps peak-to-peak
• 3 skew grades
• External feedback, internal loop filter
• Selectable positive or negative
synchronization
• Synchronous output enable
• 3-level inputs for PLL range control
• PLL bypass for DC testing
• Available in SOIC package
edge
FIGURE 2. PIN CONFIGURATION
CLKIN ¹
24 _GND
V_DDPLL
2
FSEL 3
23 _Bypass
22 nc
nc 4
21 OE
PE ⁵
V_DD
6
Q0 7
20
V_DD
19 _Q7
XRK39910
18 Q6
Q1 8
17 GND
GND ⁹
16 _Q5
Q2 ¹⁰
15 _Q4
Q3 11
V_DD
12
14
V_DD
13 FB_IN
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com