XRK39351 Datasheet, PDF (4/10 Pages) Exar Corporation – 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER

XRK39351
PRELIMINARY
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
xr
REV. P1.0.0
PIN NAME
REF_SEL
PLL_EN
SELA
SELB
SELC
SELD
OE
TABLE 1: CONTROL INPUT FUNCTION TABLE
0
1
DEFAULT
PECL clock inputs selected as reference
TCLK input selected as reference
0
PLL is bypassed. Test Mode. TCLK refer- PLL enabled. Normal operation. VCO out-
1
ence source drives the divider select blocks
put drives the divider select blocks
Bank A divider = 2
Bank A divider = 4
0
Bank B divider = 4
Bank B divider = 8
0
Bank C divider = 4
Bank C divider = 8
0
Bank D divider = 4
Bank D divider = 8
0
Outputs enabled
Outputs tri-stated, VCO running at minimum
0
frequency
DC CHARACTERISTICS (V_CC= 3.3 + 5%, T_A= -40°C TO +85°C)
SYMBOL
CHARACTERISTICS
MIN
V_CMRa ^{PECL Clock inputs common mode range}
1.2
V_PP PECL Clock peak-to-peak input voltage
500
V_IH Input voltage high
2.0
V_IL Input voltage low
V_{OH Output High Voltage}^a
2.4
V_{OL Output Low Voltage}^a
Z_OUT Output Impedance
I_IN
Input leakage current
I_{CC_PLL} Maximum PLL supply current
I_CC Maximum Quiescent supply current
V_TT Output Termination Voltage
TYP
MAX UNIT
V_CC-0.9 V
CONDITION
1000 mV
VCC+0.3 V
0.8
V
14-17
0.55
0.30
V I_OH=-24mA
V I_OL=24mA
V _IOL=12mA
Ω
3.0
V_CC÷2
+150
5.0
4
μΑ V_IN =V_CC or V_IN =GND
mA AV_CC pin
mA All V_CCQX pins
V
a. VCMR is the cross point of the differential input signal.
4