XRK39351 Datasheet, PDF (3/10 Pages) Exar Corporation – 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER

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REV. P1.0.0
PIN DESCRIPTIONS
PRELIMINARY
XRK39351
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12, 14, 16,
18, 20
13, 17, 21,
25, 29
15, 19
20, 22
23
26
27
28
30
31
32
NAME
AVCC
FB_IN
SELA
SELB
SELC
SELD
AGND
PECL
PECL
OE
VCC
QD[4:0]
GND
VCCQD
QC[1:0]
VCCQC
QB
VCCQB
QA
TCLK
PLL_EN
REF_SEL
TYPE
DESCRIPTION
Power
Power supply for PLL
Input pull-down External PLL feedback clock input
Input pull-down Selects divider value for Bank A output
Input pull-down Selects divider value for Bank B output
Input pull-down Selects divider value for Bank C outputs
Input pull-down Selects divider value for Bank D outputs
Power
PLL ground
Input
LVPECL - pos differential reference clock
Input
LVPECL - neg differential reference clock
Input pull-down Output enable/disable and device reset
Power
Power supply for core, inputs and bank A output clock
Output
Bank D clock outputs
Power
Ground
Power
Power supply for bank D output clocks
Output
Bank C clock outputs
Power
Power supply for bank C output clocks
Output
Bank B clock output
Power
Power supply for bank B output clock
Output
Bank A clock output
Input pull-down LVCMOS reference clock input
Input
pull-up Selects PLL or PLL-bypass (test mode) operation
Input pull-down Selects primary reference clock source
3