XRK39351 Datasheet, PDF (1/10 Pages) Exar Corporation – 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER

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PRELIMINARY
XRK39351
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
FEBRUARY 2006
GENERAL DESCRIPTION
The XRK39351 is a low voltage PLL based clock
driver designed for high speed clock distribution
applications.
The XRK39351 has two reference clock inputs, one
LVPECL and the other LVCMOS. The REF_SEL
input selects clock input to be used as the PLL’s
reference source.
The XRK39351 uses PLL technology to frequency
lock its outputs to the clock reference input. The
divider in the feedback path will determine the
frequency of the VCO. The XRK39351 provides 9
LVCMOS outputs that are separated into 4 banks.
Each of the separate output banks can individually
divide down the VCO output frequency. This allows
the XRK39351 to generate a variety of output-to-input
frequency ratios (1:1, 1:2, 1:4, 2:1 and 4:1). All
outputs provide LVCMOS compatible levels while
driving 50Ω terminated transmission lines.
The input reference clock can be directly applied to
the output dividers bypassing the PLL when PLL_EN
REV. P1.0.0
input is pulled low. This is a test mode intended for
system debug purposes.
The XRK39351 has an output/input frequency range
of 25MHz to 200MHz with the PLL enabled and an
input frequency range of 2MHz to 300MHz when the
PLL is disabled (test mode).
FEATURES
• 9 LVCMOS Outputs (4 banks)
• 25 - 200 MHz output frequency range
• Fully Integrated PLL
• 2.5V or 3.3V Operation
• Selectable reference clock input, LVCMOS or
LVPECL
• 150ps max output to output skew
• Pin compatible with MPC9351
• Industrial temp range: -40°C to +85°C
• 32-Lead TQFP Packaging
FIGURE 1. BLOCK DIAGRAM OF THE XRK39351
REF_SEL
TCLK
PECL
PECL
FB_IN
PLL_EN
SELA
SELB
SELC
SELD
1
0
VDD
0
Ref
PLL
1
FB
OE
÷2
0
1
÷4
0
÷8
1
0
1
0
1
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com