XR17L154 Datasheet, PDF (34/56 Pages) Exar Corporation – 3.3V PCI BUS QUAD UART

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XR17L154
3.3V PCI BUS QUAD UART
REV. 1.1.0
• RTS#/DTR# output status change interrupt is cleared by a read to the ISR register.
• CTS#/DSR# input status change interrupt is cleared by a read to the MSR register.
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TABLE 12: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF THE INTERRUPT+
LEVEL BIT-5 BIT-4 BIT-3 BIT-2 BIT-1
BIT-0
1
0
0
0
1
1
0 LSR (Receiver Line Status Register)
2
0
0
0
1
0
0 RXRDY (Received Data Ready)
3
0
0
1
1
0
0 RXRDY (Receive Data Time-out)
4
0
0
0
0
1
0 TXRDY (Transmitter Holding Register Empty)
5
0
0
0
0
0
0 MSR (Modem Status Register)
6
0
1
0
0
0
0 RXRDY (Received Xon/Xoff or Special character)
7
1
0
0
0
0
0 CTS#/DSR#, RTS#/DTR# change of state
X
0
0
0
0
0
1 None (default)
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (See Interrupt
Source Table 12).
ISR[5:4]: Interrupt Status
These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data
match of the Xon or Xoff character(s). Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until a Xon
character is received. ISR bit-5 indicates that CTS#/DSR# or RTS#/DTR# has changed state.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared
or altered). This bit will return to a logic 0 after resetting the FIFO.
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