XR17L154 Datasheet, PDF (26/56 Pages) Exar Corporation – 3.3V PCI BUS QUAD UART

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XR17L154
3.3V PCI BUS QUAD UART
REV. 1.1.0
4.4 Internal Loopback
Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback
mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored.
FIGURE 11. INTERNAL LOOP BACK
VCC
TransmitShif t
Regis ter
MC R bit-4=1
ReceiveShif t
Regis ter
VCC
RTS#
CTS#
DTR#
VCC
DSR#
RI#
CD#
OP1#
OP2#
TX[3:0]
RX [3:0]
RTS# [3:0]
CTS# [3:0]
DTR# [3:0]
DSR# [3:0]
RI# [3:0]
CD# [3:0]
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING.
The 4 sets of UART configuration registers are decoded using address lines A9 to A11 as shown below:
A11 A10
0
0
0
0
0
1
0
1
A9 ^{UART CHANNEL}
SELECTION
0
0
1
1
0
2
1
3
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