XR17L154 Datasheet, PDF (31/56 Pages) Exar Corporation – 3.3V PCI BUS QUAD UART

XR17L154
3.3V PCI BUS QUAD UART
REV. 1.1.0
4.7.1 Receiver Operation in non-FIFO Mode
FIGURE 14. RECEIVER OPERATION IN NON-FIFO MODE
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DISCONTINUED
1 6 X o r 8 X C lo c k
(8X M O D E R egister)
R e c e iv e D a ta S h ift
R e g is te r (R S R )
D a ta B it
V a lid a tio n
R e c e iv e D a ta C h a ra c te rs
R e c e iv e
D a ta B yte
and E rrors
E rror
F la g s in
L S R b its
4 :1
R e c e iv e D a ta
H o ld in g R e g is te r
(R H R )
R H R In te rru p t (IS R b it-2 )
R X F IF O
4.7.2 Receiver Operation with FIFO
FIGURE 15. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
16X or 8X Sampling
Clock (8XMODE Reg.)
64 bytes by 11-
bit wide FIFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Receive Data
FIFO
(64-byte)
Receive
Data
Data Bit
Validation
Receive Data Characters
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
Data falls to 40 ^{RTS#/DTR# re-asserts when data falls below the}
trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
FIFO Trigger=48 ^{RHR Interrupt (ISR bit-2) is programmed at}
FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
Data fills to 56 ^{RTS#/DTR# de-asserts when data fills above}
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RXFIFO1
4.8 Registers
Receive Holding Register (RHR)
The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register
(RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this
register whenever a data byte is transferred from the RSR. RHR also part of the receive FIFO of 64 bytes by
11-bit wide, 4 extra bits are for the error tags to be in LSR register. When the FIFO is enabled by FCR bit-0, it
acts as the first-out register of the FIFO as new data are put over the first-in register. The receive FIFO pointer
is bumped after the RHR register is read. Also, the error tags associated with the data byte are immediately
updated onto the line status register (LSR) bits 1-4.
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