XRT73L04A Datasheet, PDF (33/65 Pages) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

XRT73L04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
FIGURE 15. THE XRT73L04A SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS
Data
TPData
TNData
TxClk
1
1
0
TxClk_(n) is the clock signal that is of the selected
data rate frequency, E3 = 34.368 MHz, DS3 = 44.736
MHz and STS-1 = 51.84 MHz. If the Transmit Section
samples a "1" on the TPData_(n) input pin, then the
Transmit Section of the device generates a positive
polarity pulse via the TTIP_(n) and TRing_(n) output
pins across a 1:1 transformer. If the Transmit Section
samples a "1" on the TNData_(n) input pin, then the
Transmit Section of the device generates a negative
polarity pulse via the TTIP_(n) and TRing_(n) output
pins across a 1:1 transformer.
2.1.2 Accepting Single-Rail Data from the Ter-
minal Equipment
To transmit data in a Single-Rail data from the Termi-
nal Equipment, configure the XRT73L04A in the
HOST Mode.
To Configure Channel(n) to accept Single-Rail Da-
ta from the Terminal Equipment:
Write a "1" into the (SR/DR)_(n) bit-field, within Com-
mand Register CR3-(n) shown below. (Please refer
toTable 2 for the Address of the individual (n) chan-
nel.
COMMAND REGISTER CR3-(n)
D4
D3
D2
D1
D0
(SR/DR)_(n) LOSMUT_(n) RxOFF RxClk_(n)INV Reserved
1
x
x
x
x
The Transmit Section (of each channel) samples this
input pin on the falling edge of the TxClk_(n) clock
signal and encodes this data into the appropriate bi-
polar line signal across the TTIP_(n) and TRing_(n)
output pins.
NOTES:
1. In this mode, the Transmit Logic Block ignores the
TNData_(n) input pin.
2. If the Transmit Section of a given channel is config-
ured to accept Single-Rail data from the Terminal
Equipment, the B3ZS/HDB3 Encoder must be
enabled.
Figure 16 Illustrates the behavior of the TPData_(n)
and TxClk_(n) signals when the Transmit Logic Block
has been configured to accept Single-Rail data from
the Terminal Equipment.
FIGURE 16. THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SGNALS, WHILE THE TRANSMIT LOGIC BLOCK IS
ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
Data
1
1
0
TPData
TxClk
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR-
CUITRY
The on-chip Pulse-Shaping circuitry within the Trans-
mit Section of each Channel in the XRT73L04A gen-
erates pulses of the appropriate shapes and width to
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