XRT73L04A Datasheet, PDF (1/65 Pages) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

XRT73L04A
OCTOBER 2003
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
GENERAL DESCRIPTION
The XRT73L04A, 4-Channel, DS3/E3/STS-1 Line In-
terface Unit is an improved version of the XRT73L04
and consists of four independent line transmitters and
receivers integrated on a single chip designed for
DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73L04A can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73L04A performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
• Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L04
• Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
• Contains a 4-Wire Microprocessor Serial Interface
• Full Loop-Back Capability
• Transmit and Receive Power Down Modes
• Full Redundancy Support
• Uses Minimum External components
• Single +3.3V Power Supply
• 5V tolerant I/O
• -40°C to +85°C Operating Temperature Range
• Available in a Thermally Enhanced 144 pin TQFP
package
APPLICATIONS
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
• Multiplexers
• ATM Switches
FIGURE 1. XRT73L04A BLOCK DIAGRAM
E3_(n) STS-1/DS3_(n)
Host/(HW) RLOL_(n) EXClk_(n) RxOFF
RxClkINV
RTIP_(n)
RRing_(n)
REQEN_(n)
LOSTHR
SDI
SDO
SClk
CS/(SR/DR)
REGR
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
Invert
HDB3/
B3ZS
Decoder
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
MTIP_(n)
MRing_(n)
DMO_(n)
Device
Monitor
Tx
Control
Channel 0
Channel 1
Channel 2
Channel 3
Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
RxClk_(n)
RPOS_(n)
RNEG_(n)/
(LCV_(n))
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com