XRT73L04A Datasheet, PDF (11/65 Pages) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

RECEIVE INTERFACE
PIN #
NAME
80
RTIP_0
88
RTIP_1
101
RTIP_2
93
RTIP_3
82
REQEN_0
90
REQEN_1
99
REQEN_2
91
REQEN_3
110
RxClkINV
XRT73L04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
TYPE
I
I
I
DESCRIPTION
Receive TIP Input - Channel (n):
This input pin along with RRing_(n) is used to receive the bipolar line sig-
nal from the Remote DS3/E3/STS-1 Terminal.
Receive Equalization Enable Input - Channel (n):
Setting this input pin "High" enables the Internal Receive Equalizer
within Channel (n). Setting this pin "Low" disables the Internal Receive
Equalizer. The guidelines for enabling and disabling the Receive Equal-
izer are described in Section 3.2.
NOTE: This pin is ignored and should be tied to GND if the XRT73L04A
is going to be operating in the HOST Mode, (internally pulled-down).
Invert RxClk_(n) Output - Select:
The function of this pin depends upon the mode of operation.
Hardware Mode - Invert RxClk Output Select:
Setting this input pin "High" configures the Receive Section of all Chan-
nels to invert their RxClk_(n) clock output signals.
Setting this pin "Low" configures Channel(n) to output the recovered
data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of
RxClk_(n).
Setting this input pin "High" configures Channel (n) to output the recov-
ered data via the RPOS_(n) and RNEG_(n) output pins on the falling
edge of RxClk_(n).
NOTE: This pin is internally pulled “High”.
CLOCK INTERFACE
PIN #
NAME
66
EXClk_0
57
EXClk_1
115
EXClk_2
123
EXClk_3
TYPE
I
DESCRIPTION
External Reference Clock Input - Channel (n):
Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz
clock signal for DS3 applications or a 51.84 MHz clock signal for SONET
STS-1 applications.
The Channel (n) Clock Recovery PLL uses this signal as a Reference
Signal for Declaring and Clearing the Receive Loss of Lock Alarm. The
Clock recovery PLL also generates the exact clock for the LIU.
It is permissible to use the same clock that drives the TxClk_(n) input
pin.
It is permissible to operate the four Channels at different data rates.
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