XR16V2550 Datasheet, PDF(33/48 Page) Exar Corporation – HIGH PERFORMANCE DUART WITH 16-BYTE FIFO

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XR16V2550 Datasheet, PDF (33/48 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 16-BYTE FIFO

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PRELIMINARY

XR16V2550

REV. P1.0.0

HIGH PERFORMANCE DUART WITH 16-BYTE FIFO

4.11 Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write

These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL

is a 16-bit value. Then the value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must

be enabled via EFR bit-4 before it can be accessed. See Table 13 below and âSection 2.10, Programmable

Baud Rate Generator with Fractional Divisorâ on page 10.

DLD[5:4]: Sampling Rate Select

These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will

double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 13 below.

TABLE 13: SAMPLING RATE SELECT

DLD[5]

DLD[4]

SAMPLING RATE

0

0

16X

0

1

8X

1

X

4X

DLD[7:6]: Reserved

4.12 Device Identification Register (DVID) - Read Only

This register contains the device ID (0x02 for XR16V2550). Prior to reading this register, DLL and DLM should

be set to 0x00 (DLD = 0xXX).

4.13 Device Revision Register (DREV) - Read Only

This register contains the device revision information. For example, 0x01 means revision A. Prior to reading

this register, DLL and DLM should be set to 0x00 (DLD = 0xXX).

4.14 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive

character software flow control selection (see Table 14). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes

are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that

whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before

programming a new setting.

EFR[3:0]: Software Flow Control Select

Single character and dual sequential characters software flow control is supported. Combinations of software

flow control can be selected by programming these bits.

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