XR16V2550 Datasheet, PDF (22/48 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 16-BYTE FIFO

XR16V2550
PRELIMINARY
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
.
REV. P1.0.0
TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD
Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX
RX _LCR[7]=0
Stat. Int. Stat. Empty Data
CTS Int. RTS Int. Xoff Int. Sleep _{Enable Int.}
Int
Int.
Enable Enable Enable Mode
Enable Enable Enable
Enable
010
010
ISR
FCR
RD FIFOs FIFOs
0/
0/
INT
INT INT INT
Enabled Enabled
Source Source Source Source
RTS/ Xoff/Xon _Bit-3
Bit-2 Bit-1 Bit-0
CTS INT special
Status INT
WR RXFIFO RXFIFO 0/
LCR ≠ 0xBF
0/
DMA
TX
RX FIFOs
Trigger Trigger
TXFIFO TXFIFO
Trigger Trigger
Mode
Enable
FIFO FIFO Enable
Reset Reset
011
100
101
110
111
000
001
010
000
001
LCR RD/WR Divisor Set TX Set
Enable Break _Parity
Even
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
MCR RD/WR
0/
BRG
Pres-
caler
0/
IR Mode
Enable
0/
XonAny
Internal
Loop-
back
Enable
OP2#/INT (OP1#)
Output
Enable ^{IR Input}
Invert
RTS#
Output
Control
DTR#
Output
Control
LSR
RD RX FIFO THR & THR
Global TSR Empty
Error Empty
RX RX Fram- RX
Break ing Error Parity
Error
RX
Over-
run
Error
RX
Data LCR ≠ 0xBF
Ready
MSR RD
CD# RI# Input DSR# CTS#
Input
Input Input
Delta
CD#
Delta Delta Delta
RI# DSR# CTS#
SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Baud Rate Generator Divisor
Bit-6 Bit-5 Bit-4
Bit-3
Bit-6 Bit-5 Bit-4
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0 ^LCR[7]=1
LCR ≠ 0xBF
Bit-0
DLD RD/WR 0
0 4X Mode 8X Mode Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
LCR ≠ 0xBF
EFR[4] = 1
DREV RD
DVID RD
Bit-7
0
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3
0
Bit-2
0
Bit-1
1
Bit-0
0
LCR[7]=1
LCR ≠ 0xBF
DLL=0x00
DLM=0x00
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