XR16V2550 Datasheet, PDF (30/48 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 16-BYTE FIFO

XR16V2550
PRELIMINARY
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
REV. P1.0.0
MCR[2]: IrDA RX Inversion or OP1# (legacy term)
When Infrared mode is enabled (MCR[6]=1 and EFR[4]=1), this bit selects the idle state of the encoded IrDA
data. In internal loopback mode, this bit functions like the OP1# in the 16C550.
• Logic 0 = Select RX input as active-low encoded IrDA data (Idle state will be low) (default).
• Logic 1 = Select RX input as active-high encoded IrDA data (Idle state will be high).
In the Internal Loopback Mode, this bit controls the state of the modem input RI# bit in the MSR register as
shown in Figure 12.
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output.
• Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
• Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 12.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1)
• Logic 0 = Disable Xon-Any function (default).
• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the V2550 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4=1)
• Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be idling LOW. SEE”INFRARED MODE” ON
PAGE 18. To change the polarity of the IrDA data at the Rx input, see MCR[2].
MCR[7]: Clock Prescaler Select (requires EFR bit-4=1)
• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8 Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
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