XR16V2550 Datasheet, PDF (28/48 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 16-BYTE FIFO

XR16V2550
PRELIMINARY
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
REV. P1.0.0
BIT-1
0
0
1
1
BIT-0
0
1
0
1
WORD LENGTH
5 (default)
6
7
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2
0
1
1
WORD
LENGTH
5,6,7,8
5
6,7,8
STOP BIT LENGTH
(BIT TIME(S))
1 (default)
1-1/2
2
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 12 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
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