XRT8000_06 Datasheet, PDF (3/24 Pages) Exar Corporation – Clock Synchronizer/Adapter for Communications

PIN CONFIGURATION
SDO 1
SYNC 2
F_IN 3
GND 4
GND ⁵
CLK1 ⁶
V_CC 7
MSB ⁸
GND 9
18 SCLK
17 _CSB
16 _SDI
15 _VCC
14 _GND
13 _CLK2
12 _VCC
11 _LOCKDET
10 _VCC
18 Lead PDIP (0.300”)
XRT8000
SDO
SYNC
F_IN
GND
GND
CLK1
V_CC
MSB
GND
1
18
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
SCLK
CSB
SDI
V_CC
GND
CLK2
V_CC
LOCKDET
V_CC
18 Lead SOIC (Jedec, 0.300”)
PIN DESCRIPTION
Symbol
SDO
Pin#
1
SYNC
2
F_IN
3
GND
4
GND
5
CLK1
6
V_CC
7
MSB
8
GND
9
V_CC
10
LOCKDET 11
V_CC
12
CLK2
13
GND
14
V_CC
15
SDI
16
CSB
17
SCLK
18
Type
O
O
I
O
I
O
O
I
I
I
Description
Serial Data Output (Microprocessor Serial Interface). Data output from the command reg-
isters.
An 8kHz Signal SubDivided From F_IN. This output can be threestated via CR5. SYNC can
be used to synchronize other XRT8000 which are configured in slave modes.
Reference Frequency Input.
Digital Ground.
Digital Ground.
Clock 1. Output of the phase-locked loop 1.
Digital Positive Power Supply.
Master/Slave Mode Select Input. If this input is high, then the MASTER mode is selected. If
this input is low, then the SLAVE mode is enabled. This pin is internally pulled up via 100KW
resistor.
Analog Ground.
Analog Positive Supply.
Lock Detect. This output is high when both phase-locked loops are in lock and will go low if
either one of the phase locked loops loses lock.
Digital Positive Power Supply.
Clock 2. Output of the phase-locked loop 2.
Digital Ground.
Digital Positive Power Supply.
Serial Data Input (Microprocessor Serial Interface) Data input to the command registers.
Chip Select Not (Microprocessor Serial Interface) . When this input is low the data in and
out will be shifted in the appropriate registers. Internal pull up (100K).
Serial Clock Input (Microprocessor Serial Interface) . This clock will serve as a reference
to the data streams to SDI and SDO (the positive edge of SCLK is used to latch the data).
Rev. 1.11
3