XRT8000_06 Datasheet, PDF (14/24 Pages) Exar Corporation – Clock Synchronizer/Adapter for Communications

XRT8000
CR5 Register (Power On State = “00000”)
D0 : ( PL1/8) :
Select the divider by 8 for PLL1,
PL1/8 = “1” CLK1 output frequency is divided by 8.
PL1/8 = “0” CLK1 output frequency is as per table 4.
D1 : ( PL2/8) :
Select the divider by 8 for PLL2,
PL2/8 = “1” CLK2 output frequency is divided by 8.
PL2/8 = “0” CLK2 output frequency is as per table 5.
D2 : ( CLK2EN) , PLL2:
Output enable bit,
CLK2EN = “1” CLK2 output is enabled.
CLK2EN = “0” CLK2 output is Tri State D.
D3 : ( CLK1EN) , PLL1:
Output enable bit,
CLK1EN = “1” CLK1 output is enabled.
CLK1EN = “0” CLK1 output is Tri State D.
D4 : ( SYNCEN) , 8kHz SYNC enable bit:
SYNCEN = “1” SYNC output is enabled.
SYNCEN = “0” SYNC output is Tri State D.
CR6 to CR7 Register
Register reserved for future use.
CSB
SCLK
1
2
3
4
5
6
Address
7
8
9
10
11
12 13
14
15 16
Data In
SDI
SDO
R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
Data Out
HiZ
D0 D1 D2 D3 D4
D5
D6
D7
HiZ
Figure 4. Serial Processor Interface Data Structure
Note:
A3, A4 and A5 always Low.
A6 Do not care.
R/W bit = 1 for a read operation
2 for a write operation
D5, D6 and D7 always Low
SERIAL INTERFACE
The serial interface is a simple four wire interface that is
compatible with many of the microcontrollers available in
the market. This interface consists of the following
signals:
CSB
SCLK
SDI
SDO
Chip Select (Active Low)
Serial Clock Input
Serial Data Input
Serial Data Output
Rev. 1.11
14