XRT8000_06 Datasheet, PDF (12/24 Pages) Exar Corporation – Clock Synchronizer/Adapter for Communications

XRT8000
CR4 Register (Power On State = “00000”)
SEL24~SEL20:
These bits control the frequency multiplier “K” for the
PLL2, after selecting Kx56, Kx64 or DATA mode through
register CR1 (1 < K < 32).
Table 5 provides the settings for SEL24~20 bits to
generate harmonic of 56kHz, 64kHz or 1.2kHz at the
output of PLL2.
SEL24~SEL20
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
K factor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PLL2 Output Frequency (kHz)
Kx56 MODE
Kx64 MODE
DATA MODE
56
64
1.2
112
128
2.4
168
192
4.8
224
256
7.2
280
320
9.6
336
384
12
392
448
14.4
448
512
16.8
504
576
19.2
560
640
21.6
616
704
24
672
768
26.4
728
832
28.8
784
896
31.2
840
960
33.6
896
1024
36
952
1088
38.4
1008
1152
40.8
1064
1216
43.2
1120
1280
43.2
1176
1344
43.2
1232
1408
43.2
1288
1472
43.2
1344
1536
43.2
1400
1600
43.2
1456
1664
43.2
1512
1728
43.2
1568
1792
43.2
1624
1856
43.2
1680
1920
43.2
1736
1984
43.2
1792
2048
43.2
Note:
This table applies to forward or slave forward mode only
Table 5. CR4 Register
Rev. 1.11
12