XRT71D03 Datasheet, PDF (3/24 Pages) Exar Corporation – 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

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XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
FEATURES ................................................................................................................................................... 1
APPLICATIONS ............................................................................................................................................. 1
Figure 1. Block Diagram of the XRT71D03 ........................................................................................... 1
Figure 2. Pin Out of the XRT71D03 ........................................................................................................ 2
ORDERING INFORMATION ..................................................................................................................... 2
TABLE OF CONTENTS...................................................................................................................................... I
PIN DESCRIPTIONS ........................................................................................................... 3
ELECTRICAL CHARACTERISTICS ................................................................................... 9
Figure 3. Input/Output Timing ................................................................................................................ 9
Figure 4. Timing Diagram for the Microprocessor Serial Interface .................................................. 10
SYSTEM DESCRIPTION ................................................................................................... 12
Figure 5. Illustration of a typical Channel_n of the XRT71D03 configured to operate in the Hardware
Mode ........................................................................................................................................ 12
Figure 6. Illustration of a typical Channel_n of the XRT71D03 (configured to operate in the Host
Mode) ....................................................................................................................................... 13
1.0 Jitter Attenuator PLL .............................................................................................................................. 13
1.1 BACKGROUND INFORMATION DEFINITION OF JITTER ....................................................................................................13
1.2 JITTER TRANSFER CHARACTERISTICS.........................................................................................................................13
Figure 7. Category 1 DS3 Jitter Transfer Mask .................................................................................. 14
1.2.1 Jitter Tolerance .............................................................................................................................................14
1.2.2 Jitter Generation............................................................................................................................................14
1.2.3 Jitter Attenuation ...........................................................................................................................................14
1.3 XRT71D03 JITTER TRANSFER AND TOLERANCE.........................................................................................................15
TABLE 1: XRT71D03 JITTER TRANSFER FUNCTION .................................................................................. 15
Figure 8. DS3 Jitter Transfer Characteristics ..................................................................................... 16
Figure 9. E3 Jitter Transfer Characteristics ........................................................................................ 16
Figure 10. STS-1 Jitter Transfer Characteristics ................................................................................ 17
TABLE 2: XRT71D03 MAXIMUM JITTER TOLERANCE ................................................................................. 18
2.0 Operating Modes .................................................................................................................................... 19
2.1 HARDWARE MODE .....................................................................................................................................................19
TABLE 3: FUNCTIONS OF DUAL MODE PINS IN HARDWARE MODE CONFIGURATION ...................................... 19
2.2 HOST MODE.............................................................................................................................................................19
TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS ...................................................... 19
3.0 Microprocessor Serial Interface ............................................................................................................ 19
3.1 SERIAL INTERFACE OPERATION..................................................................................................................................19
3.1.1 Bit 1—R/W (Read/Write) Bit ..........................................................................................................................19
3.1.2 Bits 2 through 5—A0, A1, A2, A3, and A4 ....................................................................................................19
3.1.3 Bit 7—A5 .......................................................................................................................................................19
3.1.4 Bit 8—A6 .......................................................................................................................................................19
3.1.5 Read Operation .............................................................................................................................................19
3.1.6 Write Operation .............................................................................................................................................20
Figure 11. Microprocessor Serial Interface Data Structure ............................................................... 20
3.1.7 Simplified Interface Option ............................................................................................................................20
Figure 12. Timing Diagram for the Microprocessor Serial Interface ................................................ 21
ORDERING INFORMATION ............................................................................................. 22
PACKAGE DIMENSIONS ................................................................................................. 22
REVISION HISTORY ..................................................................................................................................... 23
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