XRT71D03 Datasheet, PDF (20/24 Pages) Exar Corporation – 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
áç
2.0 OPERATING MODES
2.1 HARDWARE MODE
The HOST pin is used to select the operating mode of
the XRT71D03. In Hardware mode (connect this pin
to ground), the serial processor interface is disabled
and hard-wired pins are used to control configuration
and report status.
TABLE 3: FUNCTIONS OF DUAL MODE PINS IN
HARDWARE MODE CONFIGURATION
PIN #
PIN NAME
FUNCTION, WHILE IN THE
HARDWARE MODE
63
DJA_1/(SDI)
DJA_1
21
DJA_0/SCLK
DJA_0
29
DJA_2(CS)
DJA_2
2.2 HOST MODE
In Host mode (connect the HOST pin to VDD), the se-
rial port interface pins are used to control configura-
tion and status report. In this mode, serial interface
pins, SDI, SDO,SCLK and CS are used.
A listing of these Command Registers, their Address-
es and their bit-formats are listed below in Table 4.
TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS
ADDR
COMMAND
REGISTER
TYPE
D7
D6
D5
D4
D3
D2
D1
D0
0X06 CR6
R/W *** *** STS-1_0 DS3/E3_0 DJA_0 RRClkES_0 RClkES_0 FSS_0
0x07 CR7
RO *** ***
***
***
***
***
FL_0
0x0E CR14 R/W *** *** STS-1_1 DS3/E3_1 DJA_1 RRClkES_1 RClkES_1 FSS_1
0x0F CR15
RO
*** ***
***
***
***
***
FL_1
0x16 CR22 R/W *** *** STS-1_2 DS3/E3_2 DJA_2 RRClkES_2 RClkES_2 FSS_2
0x17 CR23
RO
*** ***
***
***
***
***
FL_2
3.0 MICROPROCESSOR SERIAL INTERFACE
The serial interface for the XRT71D03 and the
XRT73L00 family of E3/DS3/STS-1 LIU’s are the
same, which makes it easy to configure both the
XRT71D03 and the LIU with a single CS, SDI, SDO
and SClk input and output pins.
3.1 SERIAL INTERFACE OPERATION.
Serial interface data structure and timings are provid-
ed in Figure 5 and 6 respectively.
The clock signal is provided to the SClk and the CS is
asserted for 50 ns prior to the first rising edge of the
SClk.
3.1.1 Bit 1—R/W (Read/Write) Bit
This bit will be clocked into the SDI input, on the first
rising edge of SClk (after CS has been asserted).
This bit indicates whether the current operation is a
Read or Write operation.
A “1” in this bit specifies a Read operation, a “0” in
this bit specifies a Write operation.
3.1.2 Bits 2 through 5—A0, A1, A2, A3, and A4
The five (5) bit Address Values (labeled A0, A1, A2,
A3, and A4).
The next five rising edges of the SClk signal will clock
in the 5-bit address value for this particular Read (or
Write) operation. The address selects the Command
Register for reading data from, or writing data to. The
address bits to the SDI input pin is applied in ascend-
ing order with the LSB (least significant bit) first.
3.1.3 Bit 7—A5
A5 must be set to “0”, as shown in Figure 11.
3.1.4 Bit 8—A6
The value of A6 is a don’t care.
Once these first 8 bits have been written into the Seri-
al Interface, the subsequent action depends upon
whether the current operation is a Read or Write op-
eration.
3.1.5 Read Operation
Once the last address bit (A4) has been clocked into
the SDI input, the Read operation will proceed
through an idle period, lasting three SClk periods. On
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