XRT71D00 Datasheet, PDF (3/18 Pages) Exar Corporation – E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER

XRT71D00
REV. 1.01

E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
PRELIMINARY
GENERAL DESCRIPTION ................................................................................................. 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS .............................................................................................................................................. 1
BLOCK DIAGRAM OF THE XRT71D00 ............................................................................................................ 1
PIN OUT OF THE XRT71D00 (32 LEAD TFQP PACKAGE) .............................................................................. 2
ORDERING INFORMATION ............................................................................................... 2
PIN DESCRIPTIONS .......................................................................................................... 3
ELECTRICAL CHARACTERISTICS .................................................................................. 6
SYSTEM DESCRIPTION .................................................................................................... 8
Figure 1. Illustration of the XRT71D00 ( configured to operate in the “Hardware” Mode) .....................8
Figure 2. Illustration of the XRT71D00(configured to operate in the “Host” Mode) ................................. 9
BACKGROUND INFORMATION: ........................................................................................................................ 9
Figure 3. Category 1 DS3 Jitter Transfer Mask ..........................................................................................10
JITTER ATTENUATION: .......................................................................................................................... 10
Figure 4. XRT71D00 Desynchronizer Block Diagram ................................................................................ 11
TABLE 1: FUNCTIONS OF DUAL MODE PINS IN “HARDWARE” MODE CONFIGURATION ......................................... 11
TABLE 2: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS ............................................................. 12
Figure 5. Microprocessor Serial Interface Data Structure .........................................................................13
Figure 6. Timing Diagram for the Microprocessor Serial Interface .......................................................... 13
Figure 7. Input/Output Timing ......................................................................................................................14
TABLE 3: XRT71D00 JITTER TRANSFER FUNCTION ......................................................................................... 14
TABLE 4: XRT71D00 MAXIMUM JITTER TOLERANCE ........................................................................................ 15
PACKAGE INFORMATION .............................................................................................. 16
32 LEAD TQFP PACKAGE DIMENSIONS ....................................................................................... 16
ORDERING INFORMATION ............................................................................................................. 16
REVISIONS ....................................................................................................................... 17
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