XRT71D00 Datasheet, PDF (14/18 Pages) Exar Corporation – E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER


E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER
XRT71D00
REV. 1.01
FIGURE 5. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
R/W A0 A1 A2 A3 A4 0 A6 D0 D1 D2 D3 D4 D5 D6 D7
High Z
High Z
D0 D1 D2 D3 D4 D5 D6 D7
NOTES:
1. A5 is always “0”.
2. R/W = “1” for “Read” Operations
3. R/W = “0” for “Write” Operations
4. Denotes a “don’t care” value (shaded areas)
SIMPLIFIED INTERFACE OPTION
The user can simplify the design of the circuitry con-
necting to the Microprocessor Serial Interface by ty-
ing both the SDO and SDI pins together, and reading
data from and/or writing data to this “combined” sig-
nal. This simplification is possible because only one
of these signals are active at any given time. The in-
active signal will be tri-stated.
FIGURE 6. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
CS
SClk
SDI
t21
t22
t23
t24
R/W
t27
t25
t26
A0
A1
t29
t28
CS
SClk
t30
t31
SDO _Hi-Z
D0
D1
Hi-Z
SDI
t33
D2
t32
D7
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