XRT71D00 Datasheet, PDF (13/18 Pages) Exar Corporation – E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER

XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER

REV. 1.01
TABLE 2: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS
ADDR
COMMAND CH_ADDR CH_ADDR
REGISTER _1
_0
TYPE
0X06 CR6
0
0x07 CR7
0
0x0E CR14
0
0x0F CR15
0
0x16 CR22
1
0x17 CR22
1
0
R/W
0
RO
1
R/W
1
RO
0
R/W
0
RO
D6
STS-1
***
STS-1
***
STS-1
***
D5
D4
D3
0 E3/DS3* DJA
***
***
***
0 E3/DS3* DJA
***
***
***
0 E3/DS3* DJA
***
***
***
D2
D1
D0
BWS ClkES FSS
***
***
FL
BWS ClkES FSS
***
***
FL
BWS ClkES FSS
***
***
FL
• The serial interface for both the XRT71D00 and the
XRT7300, XRT7302 and XRT7303, E3/DS3/STS-1
LIU which makes it easy to configure both the
XRT71D00 and the LIU with a single CS, SDI, SDO
and SClk input and output pins.
SERIAL INTERFACE OPERATION.
Serial interface data structure and timings are provid-
ed in Figure 5 and 6 respectively..
The clock signal is provided to the SClk and the CS is
asserted for 50 ns prior to the first rising edge of the
SClk.
BIT 1—“R/W” (READ/WRITE) BIT
This bit will be clocked into the SDI input, on the first
rising edge of SClk (after CS has been asserted).
This bit indicates whether the current operation is a
“Read” or “Write” operation. A “1” in this bit specifies
a “Read” operation; whereas, a “0” in this bit specifies
a “Write” operation.
Bits 2 through 5: The five (5) bit Address Values (la-
beled A0, A1, A2 ,A3,and A4)
The next four rising edges of the SClk signal will clock
in the 5-bit address value for this particular Read (or
Write) operation. The address selects the Command
Register for reading data from, or writing data to. The
address bits to the SDI input pin is applied in ascend-
ing order with the LSB (least significant bit) first.
BIT 7:
A5 must be set to “0”, as shown in Figure 5.
BIT 8—A6
The value of “A6” is a “don’t care”.
Once these first 8 bits have been written into the Seri-
al Interface, the subsequent action depends upon
whether the current operation is a “Read” or “Write”
operation.
READ OPERATION
Once the last address bit (A4) has been clocked into
the SDI input, the “Read” operation will proceed
through an idle period, lasting three SClk periods. On
the falling edge of SClk Cycle #8 (see Figure 5) the
serial data output signal (SDO) becomes active. At
this point the user can begin reading the data con-
tents of the addressed Command Register (at Ad-
dress [A4,A3, A2, A1, A0]) via the SDO output pin.
The Serial Interface will output this seven bit data
word (D0 through D6) in ascending order (with the
LSB first), on the falling edges of the SClk . The data
(on the SDO output pin) is stable for reading on the
very next rising edge of the SClk .
WRITE OPERATION
Once the last address bit (A4) has been clocked into
the SDI input, the “Write” operation will proceed
through an idle period, lasting three SClk periods. Pri-
or to the rising edge of SClk Cycle #9 , eight bit data
word is applied to SDI input. Data on SDI is latched
on the rising edge of SClk.
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