XR16M2650 Datasheet, PDF (3/47 Pages) Exar Corporation – HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO

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PIN DESCRIPTIONS
XR16M2650
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO
Pin Description
NAME
32-QFN
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
18
26
A1
19
27
A0
20
28
D7
2
3
D6
1
2
D5
32
1
D4
31
48
D3
30
47
D2
29
46
D1
28
45
D0
27
44
IOR#
14
19
IOW#
12
15
CSA#
7
10
CSB#
8
11
INTA
22
30
INTB
21
29
TXRDYA#
-
43
RXRDYA#
-
31
TXRDYB#
-
6
I _{Address data lines [2:0]. These 3 address lines select one of the inter-}
nal registers in UART channel A/B during a data bus transaction.
I/O _{Data bus lines [7:0] (bidirectional).}
I _{Input/Output Read Strobe (active low). The falling edge instigates an}
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
I _{Input/Output Write Strobe (active low). The falling edge instigates an}
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
I _{UART channel A select (active low) to enable UART channel A in the}
device for data bus operation.
I _{UART channel B select (active low) to enable UART channel B in the}
device for data bus operation.
O _{UART channel A Interrupt output. The output state is defined by the}
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output LOW when MCR[3] is set to HIGH. INTA is
set to the three state mode and OP2A# output HIGH when MCR[3] is
set to LOW (default). See MCR[3].
O _{UART channel B Interrupt output. The output state is defined by the}
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output LOW when MCR[3] is set to HIGH. INTB is
set to the three state mode and OP2B# output HIGH when MCR[3] is
set to LOW (default). See MCR[3].
O _{UART channel A Transmitter Ready (active low). The output provides}
the TX FIFO/THR status for transmit channel A. See Table 2. If it is not
used, leave it unconnected.
O _{UART channel A Receiver Ready (active low). This output provides the}
RX FIFO/RHR status for receive channel A. See Table 2. If it is not
used, leave it unconnected.
O _{UART channel B Transmitter Ready (active low). The output provides}
the TX FIFO/THR status for transmit channel B. See Table 3. If it is not
used, leave it unconnected.
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