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XR16M2650 Datasheet, PDF (27/47 Pages) Exar Corporation – HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO
XR16M2650
REV. 1.0.2
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 11 below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 11 shows the complete selections.
TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
0
0
1
1
FCR
BIT-6
0
1
0
1
FCR
BIT-5
0
0
1
1
FCR
RECEIVE
BIT-4 TRIGGER LEVEL
0
1
0
1
8 (default)
16
24
28
TRANSMIT
TRIGGER
LEVEL
16 (default)
8
24
30
COMPATIBILITY
16C550, 16C2550,
16C2552, 16C554,
16C580 compatible.
4.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
0
0
1
1
BIT-0
0
1
0
1
WORD LENGTH
5 (default)
6
7
8
27