XR-T7295 Datasheet, PDF (3/20 Pages) Exar Corporation – DS3/Sonet STS-1 Integrated Line Receiver

XR-T7295
PIN CONFIGURATION
GNDA 1
R_IN 2
TMC1 ³
LPF1 ⁴
LPF2 5
TMC2 ⁶
RLOS ⁷
RLOL 8
GNDD 9
GNDC ₁₀
20 V_DDA
19 LOSTHR
18 _REQB
17 _ICT
16 _RPDATA
15 _RNDATA
14 _RCLK
13 _EXCLK
12 _VDDC
11 _VDDD
20 Lead PDIP (0.300”)
GNDA
R_IN
TMC1
LPF1
LPF2
TMC2
RLOS
RLOL
GNDD
GNDC
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V_DDA
LOSTHR
REQB
ICT
RPDATA
RNDATA
RCLK
EXCLK
V_DDC
V_DDD
20 Lead SOJ (Jedec, 0.300”)
PIN DESCRIPTION
Pin #
1
2
3,6
4,5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
GNDA
R_IN
TMC1-TMC2
LPF1-LPF2
RLOS
RLOL
GNDD
GNDC
V_DDD
V_DDC
EXCLK
RCLK
RNDATA
RPDATA
ICT
REQB
LOSTHR
V_DDA
Type
I
I
I
O
O
I
O
O
O
I
I
I
Description
Analog Ground.
Receive Input. Analog receive input. This pin is internally biased at about 1.5V in series
with 50 kΩ.
Test Mode Control 1 and 2. Internal test modes are enabled within the device by using
TMC1 and TMC2. Users must tie these pins to the ground plane.
PLL Filter 1 and 2. An external capacitor (0.1µF $20%) is connected between these pins.
Receive Loss-of-signal. This pin us set high on loss of the data signal at the receive input.
(See Table 7)
Receive PLL Loss-of-lock. This pin is set high on loss of PLL frequency lock.
Digital Ground for PLL Clock. Ground lead for all circuitry running synchronously with
PLL clock.
Digital Ground for EXCLK. Ground lead for all circuitry running synchronously with
EXCLK.
5V Digital Supply ($10%) for PLL Clock. Power for all circuitry running synchronously
with PLL clock.
5V Digital Supply ($10%) for EXCLK. Power for all circuitry running synchronously with
EXCLK.
External Reference Clock. A valid DS3 (44.736MHz $100ppm) or STS-1 (51.84MHz +
100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to V_DD
/2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns.
Receive Clock. Recovered clock signal to the terminal equipment.
Receive Negative Data. Negative pulse data output to the terminal equipment. (See
Figure 11.)
Receive Positive Data. Positive pulse data output to the terminal equipment. (See
Figure 11)
In-circuit Test Control (Active-low). If ICT is forced low, all digital output pins (RCLK,
RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-cir-
cuit testing. There is an internal pull-up on this pin.
Receive Equalization Bypass. A high on this pin bypasses the internal equalizer. A low
places the equalizer in the data path.
Loss-of-signal Threshold Control. The voltage forced on this pin controls the input loss-
of-signal threshold. Three settings are provided by forcing GND, V_DD/2, or V_DD. This pin
must be set to the desired level upon power-up and should not be changed during opera-
tion.
5V Analog Supply ($10%).
Rev. 1.05
3