XR-T7295 Datasheet, PDF (12/20 Pages) Exar Corporation – DS3/Sonet STS-1 Integrated Line Receiver

XR-T7295
A high RLOL output indicates that the acquisition circuit is
working to bring the PLL into proper frequency lock.
RLOL remains high until frequency lock has occurred;
however, the minimum RLOL pulse width is 32 clock
cycles.
PHASE HITS
In response to a phase hit in the input data, the XR-T7295
returns to error free operation in less than 2ms. During
the requisition time, RLOS may temporarily be indicated.
LOSS-OF-SIGNAL DETECTION
Figure 1 shows that analog and digital methods of
loss-of-signal (LOS) detection are combined to create the
RLOS alarm output. RLOS is set if either the analog or
digital detection circuitry indicates LOS has occurred.
ANALOG DETECTION
The analog LOS detector monitors the peak input signal
amplitude. RLOS makes a high-to-low transition (input
signal regained) when the input signal amplitude exceeds
the loss-of signal threshold defined in Table 7. The RLOS
low-to-high transition (input signal loss) occurs at a level
typically 1.0 dB below the high-to-low transition level. The
hysteresis prevents RLOS chattering. Once set, the
RLOS alarm remains high for at least 32 clock cycles,
allowing for system detection of a LOS condition without
the use of an external latch.
To allow for varying levels of noise and crosstalk in
different applications, three loss-of-signal threshold
settings are available using the LOSTHR pin. Setting
LOSTHR = V_DD provides the lowest loss-of-signal
threshold; LOSTHR = V_DD/2 (can be produced using two
50 kΩ $10% resistors as a voltage divider between
V_DDD and GNDD) provides an intermediate threshold;
and LOSTHR = GND provides the highest threshold. The
LOSTHR pin must be set to its desired value at power-up
and must not be changed during operation.
DIGITAL DETECTION
In addition to the signal amplitude monitoring of the
analog LOS detector, the digital LOS detector monitors
the recovered data 1s density. The RLOS alarm goes
high if 160 $32 or more consecutive 0s occur in the
receive data stream. The alarm goes low when at least
ten 1s occur in a string of 32 consecutive bits. This
hysteresis prevents RLOS chattering and guarantees a
minimum RLOS pulse width of 32 clock cycles. Note,
however, that RLOS chatter can still occur. When
REQB=1, input signal levels above the analog RLOS
threshold can still be low enough to result in a high bit error
rate. The resultant data stream (containing) errors can
temporarily activate the digital LOS detector, and RLOS
chatter can occur. Therefore, RLOS should not be used
as a bit error rate monitor.
RLOS chatter can also occur when RLOL is activated
(high).
Rev. 1.05
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