XR-T7295 Datasheet, PDF (11/20 Pages) Exar Corporation – DS3/Sonet STS-1 Integrated Line Receiver

XR-T7295
JITTER ACCOMMODATION
LOSS-OF-LOCK DETECTION
Under all allowable operating conditions, the jitter
accommodation of the XR-T7295 device exceeds all
system requirements for error-free operation
(BER<1E^-9). The typical (V_DD = 5V, T = 25°C, DSX-3
nominal signal level) jitter accommodation for the
XR-T7295 is shown in Figure 10.
FALSE-LOCK IMMUNITY
False-lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a frequency
not equal to the incoming data rate. The XR-T7295
device uses a combination frequency/phase-lock
architecture to prevent false-lock. An on-chip frequency
comparator continuously compares the EXCLK reference
to the PLL clock. If the frequency difference between the
EXCLK and PLL clock exceeds approximately $0.5%,
correction circuitry forces re-acquisition of the proper
frequency and phase.
ACQUISITION TIME
If a valid input signal is assumed to be already present at
R_IN, the maximum time between the application of device
power and error-free operation is 20ms. If power has
already been applied, the interval between the application
of valid data (or the action of valid data following a loss of
signal) and error-free operation is 4ms.
As stated above, the PLL acquisition aid circuitry monitors
the PLL clock frequency relative to the EXCLK frequency.
The RLOL alarm is activated if the difference between the
PLL clock and the EXCLK frequency exceeds
approximately $0.5%.
This will not occur until at least 250 bit periods after loss of
input data.
-----5432110^{ÎÎÎÎÎÎÎÎÎ}₁₀₀^{ÎÎÎÎÎÎÎÎÎ}₅^{ÎÎÎÎÎÎÎÎÎ}_0P0E^{ÎÎÎÎÎÎÎÎÎ}_1AKK^{ÎÎÎÎÎÎÎÎÎ= 0ÎÎÎÎÎÎÎÎÎ.055KdÎÎÎÎÎÎÎÎÎB1f30dKÎÎÎÎÎÎÎÎÎB =ÎÎÎÎÎÎÎÎÎ25005KÎÎÎÎÎÎÎÎÎk1H0z0ÎÎÎÎÎÎÎÎÎ}_K ^{ÎÎÎÎÎÎÎÎÎ}_500K
Frequency (Hz)
Figure 9. Typical PLL Jitter Transfer
Characteristic
411000..01^{ÎÎÎÎÎÎÎÎÎÎÎ}₁^{ÎÎÎÎÎÎÎÎÎÎÎ}_G.8^{ÎÎÎÎÎÎÎÎÎÎÎ}₂₄ ^{ÎÎÎÎÎÎÎÎÎÎÎ}₁^{ÎÎÎÎÎÎÎÎÎÎÎ}_{0 ÎÎT}^{ÎÎÎÎÎÎÎÎÎ}_{RC-TaÎÎÎÎÎÎÎÎÎÎÎSteYg-PoÎÎ0ÎÎÎÎÎÎÎÎÎ1rU00y0B01T4ÎÎÎÎÎÎÎÎÎÎÎ59R49C-0TaÎÎ1}^{ÎÎÎÎÎÎÎÎÎ}Ste4Yg-o0_{ÎÎÎÎÎÎÎÎÎÎÎr0y0124K9}^{ÎÎÎÎÎÎÎÎÎÎÎ}9 ^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}₁^{ÎÎÎÎÎÎÎÎÎÎÎ}_{0K ÎÎÎÎÎÎÎÎÎÎÎXÎÎÎÎÎÎÎÎÎÎÎR-T1ÎÎ7}^{ÎÎÎÎÎÎÎÎÎ}_{0209K5ÎÎÎÎÎÎÎÎÎÎÎTypÎÎÎÎÎÎÎÎÎÎÎical}^{ÎÎÎÎÎÎÎÎÎÎÎ}₁₀₀^{ÎÎÎÎÎÎÎÎÎÎÎ}_0K
ÎÎÎÎÎÎÎÎ _{XR-T7295 Typical}
ÎÎÎÎÎÎÎÎ _Jitter
ÎÎÎÎÎÎÎÎ _Frequency
(Hz)
Jitter
Amplitude
(U.I.)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _5k
10
ÎÎÎÎÎÎÎÎ 10k
5
60k
1
ÎÎÎÎÎÎÎÎ _300k
0.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _1M
0.4
Sinewave Jitter Frequency (Hz)
Figure 10. Input Jitter Tolerance at DSX-3 Level
Rev. 1.05
11