XRD9836 Datasheet, PDF(29/32 Page) Exar Corporation

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XRD9836 Datasheet, PDF (29/32 Pages) Exar Corporation – 16-BIT PIXEL GAIN AFE

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XRD9836

16-BIT PIXEL GAIN AFE

REV. 1.0.0

APPLICATION NOTES AND SCHEMAT-

ICS

See Figure 23 for a typical CCD application hookup.

The diagram shows an interface to a standard 3

channel output CCD. Both the ADC Output and OGI

Control are parallel interfaces to the system ASIC

controller. The timing inputs are provided by the sys-

tem ASIC or timing generator (TG). The serial port

control is typically sourced from a micro processor or

the system ASIC.

It is recommended that all AGND, DGND and OGND

pins, be connected to the analog ground plane under

the XRD9836. All VDDâs should be supplied from a

low noise, well filtered regulator which derives the

power supply voltage from the CCD power supply. All

of the AVDD pins are analog power supplies and

should be decoupled locally to the nearest ground pin

with at 0.1uF, high frequency capacitor. The DVDD

and OVDD power pins should be locally decoupled to

the nearest ground pin also. DVDD and OVDD should

be connected to the same power supply network as

the digital ASCI which receives data from the

XRD9836.

CCD

It is recommended that each

15V

0.1uf

1uf

power pin be decoupled to

ground with capacitors placed

as close to power pin as

VDD3A VDD3D

possible.

1nf

10K

(timing generator)

ASIC

RED+

RED-

GRN+

GRN-

BLU+

BLU-

REXT

AAA

VVV

DDD

D OO

V VV

D DD

ADCO7

ADCO6

ADCO5

ADCO4

ADCO3

ADCO2

ADCO1

ADCO0

9836

OGI9

OGI8

OGI7

OGI6

OGI5

OGI4

OGI3

OGI2

OGI1

OGI0

ADCCLKK

VSAMP

BSAMP

LCLMP

CAPP

CAPN

LOAD

SCLK A A A

O O CMREF

SDIO G G G G G G

NNN N NN

DDD D DD

ADC

OUTPUT

BUS

ASIC

OGI

CONTROL

FIGURE 23. TYPICAL CCD APPLICATION DIAGRAM FOR THE XRD9836

The XRD9836 has an input range limitation of 1V

maximum for a CCD input. If the maximum CCD out-

put signal swing is greater than 1V, a resisitive divider

network on the inputs can be used to reduce the CCD

output to meet the 1V input max requirement of the

XRD9836 inputs. See Figure 24 for a typical imple-

mentation of a resistor divider. Each input channel will

require a matching divider network.

CCD

15V

Vin

C1 1nf

Vsig

C2 1nf

XRD9836

RED+

RED -

Vin = Vsig(R1/(R1+R2))

FIGURE 24. INPUT RESISTIVE DIVIDER NETWORK

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