XRD9836 Datasheet, PDF (23/32 Pages) Exar Corporation – 16-BIT PIXEL GAIN AFE

xr
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
Control / Polarity
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Register
CNTRL / POL
(01111)
default
ADC
POL
0
LCLMP
POL
0
BSAMP
POL
0
VSAMP
POL
DLP
DISABLE
PWRDWN
0
0
0
OEB
0
RESET
0
The CNTRL / POL register is used to program various options including: input timing polarity control, dynamic low
power disable, power down for the chip, output enable, and reset. Reset will reset ALL registers including reset.
All the clock inputs (except the serial interface SCLK) can be programmed to be active high or active low. See the “Tim-
ing” section for more information. ADCpol, LCLMPpol, BSAMPpol, and VSAMPpol set the polarity of ADCLK, LCLMP,
BSAMP, and VSAMP respectively.
ADCpol - Sets the polarity of the ADCLK input. ADCpol = 0, ADCLK low during VSAMP. ADCpol = 0, ADCLK inverted
so that it is high during VSAMP.
LCLMPpol - Sets the polarity of the LCLMP input. LCLMPpol = 0, LCMLP is active high during clamping operation and
odd pixel determined from falling edge.
BSAMPpol - Sets the polarity of the BSAMP input. BSAMPpol = 0, BSAMP is active high. The CCD black level is sam-
ple by the falling edge. BSAMPpol = 1, BSAMP is active low. The CCD black level is sample by the rising edge.
VSAMPpol - Sets the polarity of the VSAMP input. VSAMPpol = 0, VSAMP is active high. The CCD video level is sam-
ple by the falling edge. VSAMPpol = 1, VSAMP is active low. The CCD video level is sample by the rising edge.
DLP DISABLE (ADC Dynamic Low Power Disable)
PWRDWN - Puts the XRD9836 into power down state. PWRDWN = 0, normal operation. PWRDWN = 1, low power
state.
OEB - Enables the ADCDO bus. OEB = 0, data valid on ADCDO bus. OEB = 1, ADCDO bus high impedance.
RESET - Will reset the XRD9836 to default (power up) conditions. RESET = 0, normal operation. RESET = 1, all inter-
nal registers set to default values and clears itself after ~ 10ns.
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