XRD9836 Datasheet, PDF (24/32 Pages) Exar Corporation – 16-BIT PIXEL GAIN AFE

XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
xr
Delay
Registers
DelayA
(10000)
default
DelayB
(10001)
default
DelayC
(10010)
default
DelayD
(10011)
default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DelayA
[7]
1
DelayB
[7]
0
DelayC
[7]
0
DelayD
[7]
0
DelayA
[6]
0
DelayB
[6]
0
DelayC
[6]
0
DelayD
[6]
0
DelayA
[5]
0
DelayB
[5]
0
DelayC
[5]
0
DelayD
[5]
0
DelayA
[4]
0
DelayB
[4]
0
DelayC
[4]
0
DelayD
[4]
0
DelayA
[3]
0
DelayB
[3]
0
DelayC
[3]
0
DelayD
[3]
0
DelayA
[2]
0
DelayB
[2]
0
DelayC
[2]
0
DelayD
[2]
0
DelayA
[1]
0
DelayB
[1]
0
DelayC
[1]
0
DelayD
[1]
0
DelayA
[0]
0
DelayB
[0]
0
DelayC
[0]
0
DelayD
[0]
0
DelayA[7:4] - Controls the OGI_DLY. These bits are used to program the timing delay of the ADCLK used to sample the
Offset-Gain-Inputs (OGI). Code 0000 is delay of 0ns, and code 1111 is 15ns. Default is 1000 = 7 ns. OGI_DLY should
be larger than VSAMP_OGI_DLY.
DelayA[3:0] - Controls the ADCO_DLY. These bits are used to program the timing delay of ADCO outputs in relation to
ADCLK. Code 0000 is delay of 0ns, and code 1111 is 15ns. Default is 0000 = 0ns. This is used to adjust setup and hold
times of the output, for the ASIC chip.
DelayB[7:4] - Controls the BSAMP_LEADING_EDGE_DLY. These bits set the delay for the leading edge of the internal
BSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayB[3:0] - Controls the BSAMP_TRAILING_EDGE_DLY. These bits set the delay for the trailing edge of the internal
BSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayC[7:4] - Controls the VSAMP_LEADING_EDGE_DLY. These bits set the delay for the leading edge of the internal
VSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayC[3:0] - Controls the VSAMP_TRAILING_EDGE_DLY. These bits set the delay for the trailing edge of the internal
VSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayD[7:4] - Controls the VSAMP_OGI_DLY. These bits set the delay for the internal VSAMP that is used to transfer
the OGI register data to the PGA & OFFSET control registers.
DelayD[3:0] - Controls the ADC_DLY. These bits set the delay of the internal clock used for ADC operation. Code 0000
is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
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