XRD9836 Datasheet, PDF(11/32 Page) Exar Corporation

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XRD9836 Datasheet, PDF (11/32 Pages) Exar Corporation – 16-BIT PIXEL GAIN AFE

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XRD9836

16-BIT PIXEL GAIN AFE

REV. 1.0.0

GAIN SELECT:

The XRD9836âs Gain range is selectable to either 1 to

10 or 2 to 20 with the Gain Select Bit. If Gain of 1 to

10 is selected (Gain Select bit = 0), the maximum in-

put is 1.0V. If Gain of 2 to 20 is selected (Gain Select

bit = 1), the maximum input is 0.5V.

PARALLEL PORT FOR PIXEL OFFSET

AND GAIN CONTROL (OGI):

The timing diagram in Figure 4 shows the Offset and

Gain Inputs (OGI) and ADCLK in relationship to

VSAMP.

VSAMP

3 - Channel OGI Timing

Tev

Tva

ADCLK

OGI 10-bit

parallel input

Togis

Togih

VSAMP

ADCLK

OGI 10-bit

parallel input

1 - Channel OGI Timing

Tev

Tva

Gain

Togis

Offset

Gain

Togih

FIGURE 4. OGI TIMING (ADCLKPOL=0, VSAMPPOL=0)

The ASIC chip will be clocking OGI data at six times

the pixel rate clock in 3-CH mode and two times the

pixel rate in 1-CH mode. The gain data is grabbed on

the rising edge of ADCLK and the offset data on the

falling edge of ADCLK. The OGI port is read into in-

ternal pixel gain and offset registers only when Input

Enable (IE) is active before the sampling edge of

VSAMP as shown above. As noted the RGB gain/off-

set data is synchronized to sampling edge of VSAMP.

Note that ADCLK frequency is 3X the pixel rate in 3-

CH mode and 1X the pixel rate in 1-CH mode. The

ADCLKâs duty cycle is required to be 50%. It is as-

sumed that the OGI port and ADCLK input have

matched output drivers inside the ASIC, matched

trace lengths on the PCB between the ASIC and the

XRD9836, and matched delays at input buffers inside

the XRD9836 in order to receive OGI data on both

edges of ADCLK error free.

The latency between the input of the parallel inputs

and their effective application is 1 pixel. The user is

also reminded that data coming out of the ADC out-

puts will have latency from the gain and offset provid-

ed (10 ADC cycles for single color and 12 cycles for

3-color). This latency includes the cycles to put the

gain and offset data into the registers and the latency

of the ADC itself (9 ADCLK cycles).

Sampling of the OGI parallel input port is defined as

the red gain data being the first pulse of ADCLK after

VSAMP, therefor VSAMP must occur before a rising

edge of ADCLK. It is also recommended that

VSAMP__OGI_DLY (DelayD[7:4]) should be smaller

than OGI_DLY (DelayA[7:4]) to make sure the correct

data is sampled, and that relationship is not reversed

internally.

PARALLEL PORT FOR ADC OUTPUT

(ADCDO):

The timing diagram, Figure 5, shows the ADC output

(ADCDO). The XRD9836 will be clocking ADC high

order bytes on the rising edge of ADCLK and clocking

ADC low order bytes on the falling edge of ADCLK.

As noted the RGB data is synchronized to sampling

edge of VSAMP.

3 - Channel ADCDO Timing

VSAMP

ADCLK

ADCDO 8-bit

parallel output

BDL RDH RDL GDH GDL BDH BDL

Tadcdo

VSAMP

ADCLK

ADCDO 8-bit

parallel output

1 - Channel ADCDO Timing

Tadcdo

FIGURE 5. ADCDO TIMING (ADCLKPOL=0, VSAMPPOL=0)

PIXEL GAIN/OFFSET CONTROL (FGOM

OR PGOM):

Figure 6 shows the block diagram of the CDS/PGA/

Offset DACs/ADC signal path. The offset for each

channel is controlled by a 10-bit Dynamic offset DAC

before the CDS amplifier and a 10-bit Fine offset DAC

after the PGA amplifier. Thus, the total offset of each

channel is controlled by two 10-bit offset DACs. The

Dynamic offset DAC will have a range of -80mV to

+160mV, with the ability to adjust the CDS stage off-

set to within +/- 0.25mV. The Fine offset DAC will

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