XR28V384IM48-0A-EB Datasheet, PDF (28/42 Pages) Exar Corporation – XR28V384 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
2.2 UART Internal Registers
The UART register set for the V384 is shown in Table 10 and Table 11.
TABLE 10: UART INTERNAL REGISTERS
OFFSET
ADDRESSES
REGISTER
RESET STATE
COMMENTS
16C550 COMPATIBLE REGISTERS
0x0
DLL - Divisor LSB Register
0x1
DLM - Divisor MSB Register
0x01
0x00
LCR[7] = 1
0x0
RHR - Receive Holding Register
THR - Transmit Holding Register
0x1
IER - Interrupt Enable Register
0xXX
0xXX
0x00
LCR[7] = 0
0x2
ISR - Interrupt Status Register
FCR - FIFO Control Register
0x01
0x00
0x3
LCR - Line Control Register
0x00
0x4
MCR - Modem Control Register
0x00
0x5
LSR - Line Status Register
0x60
0x6
MSR - Modem Status Register
Bits 3:0 = 0
Bts 7-4 = Logic
Levels of the inputs
inverted
0x7
SPR - Scratch Pad Register
0x00
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