XR28V384IM48-0A-EB Datasheet, PDF (1/42 Pages) Exar Corporation – XR28V384 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
3.3V QUAD LPC UART WITH 128-BYTE FIFO
NOVEMBER 2013
REV. 1.0.0
GENERAL DESCRIPTION
The XR28V384 (V384) is a quad Universal
Asynchronous Receiver and Transmitter (UART) for
the Intel Low Pin Count (LPC) bus interface. This
device can replace or supplement a Super I/O device
to add additional serial ports to the system.
The V384 UARTs support any 16-bit I/O address
supported by the system. The register set is based on
the industry standard 16550 UART, so the V384
operates with the standard serial port drivers without
requiring a custom driver to be installed.
The 128 byte Transmit and Receive FIFOs reduce
CPU overhead and minimize the chance of buffer
overflow and data loss. In addition to the 16550
UART registers, there are also Configuration register
set where enhanced features such as the 9-bit
(multidrop) mode, IrDA mode and the Watchdog
Timer can be enabled.
The V384 is available in a 48-pin TQFP package.
APPLICATIONS
x Industrial and Embedded PCs
x Factory Automation and Process Controls
x Network Routers
x System Board Designs
FEATURES
x 128 Byte Transmit and Receive FIFO
x Compliant to LPC 1.1 Specifications
x -40°C to +85°C Industrial Temp Operation
x Watchdog Timer with WDTOUT# signal
x 4 Independent UART channels
■ Programmable I/O mapped base addresses
■ Data rates up to 3 Mbps
■ Selectable RX FIFO interrupt trigger levels
■ Auto RS-485 Half-Duplex Control mode
■ Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
■ IrDA mode and separate IRTXA# and IRRXA#
pins for the first UART channel
■ 9-bit (Multidrop) mode
x External 24MHz/48MHz clock
x Single 3.3V Supply Voltage ( ±10% )
x 5V tolerant inputs
x 48-TQFP package (7mm x 7mm)
FIGURE 1. XR28V384 BLOCK DIAGRAM
VCC
GND
P C IR S T #
LCLK
LFR AM E
#
LA D [3:0]
S E R IR Q
W DTOUT
#
CLKI
N
3.3V ± 10%
LPC
Bus
In te rfa c e
G lo b a l
C o n fig u ra tio n
R e g iste rs
W atch
Dog
T im e r
C lo ck
D ivid e r
Baud
R ate
G enerator
S tatus and
C ontrol
R e g iste rs
T X F IF O
(IrD A E ncod er)
R X F IF O
(IrD A D ecoder)
M odem
IO s
UART Channel A
Baud
R ate
G enerator
S tatus and
C ontrol
R e g iste rs
T X F IF O
R X F IF O
M odem
IO s
UART Channel B
Baud
R ate
G enerator
S tatus and
C ontrol
R e g iste rs
T X F IF O
R X F IF O
M odem
IO s
UART Channel C
Baud
R ate
G enerator
S tatus and
C ontrol
R e g iste rs
T X F IF O
R X F IF O
M odem
IO s
UART Channel D
T X A /P S _3F 8_IR Q A
IR T X A #
RXA
IR R X A #
R T S A #/P S _C O N F _2E /R S 485
D T R A #/P S _3E 0_IR Q A
C T S A #, D S R A #, C D A #, R IA #
T X B /P S _2F 8_IR Q B
RXB
R T S B #/P S _C O N F _K E Y 1/R S 485
D T R B #/P S _2E 0_IR Q B
C T S B #, D S R B #, C D B #, R IB #
T X C /P S _3E 8_IR Q C
RXC
R T S C #/P S _C O N F _K E Y 0/R S 485
D T R C #/P S _W D T
C T S C #, D S R C #, C D C #, R IC #
T X D /P S _2E 8_IR Q D
RXD
R T S D #/R S 485
DTRD#
CTSD#, DSRD#, CDD#,
R ID #
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